[b01lers2020]Welcome to Earth 1

功能测试

不知道这道题想干嘛
首先是这个界面
在这里插入图片描述
过几秒后跳到/die/
在这里插入图片描述

按指引一步步寻找

这里使用插件findsomething
在这里插入图片描述
访问/chase/在这里插入图片描述
会瞬间跳转到/die/
开burp暂停到该页面继续使用findsomething在这里插入图片描述
访问/leftt/在这里插入图片描述
访问/shoot/在这里插入图片描述
访问/door/在这里插入图片描述
访问/open/在这里插入图片描述
访问/fight/在这里插入图片描述

flag排序

访问/static/js/fight.js在这里插入图片描述
排序脚本

from itertools import permutations

flag = ["{hey", "_boy", "aaaa", "s_im", "ck!}", "_baa", "aaaa", "pctf"]

item = permutations(flag)
for i in item:
    k = ''.join(list(i))
    if k.startswith('pctf{hey_boys') and k[-1] == '}':
       print(k)

结果,咱也不敢问为什么是这样在这里插入图片描述

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Here is an example of a Verilog code for a 3-to-1 arbitration circuit: module arbiter(input [2:0] req, // Three request signals input clk, // Clock output reg grant); // Grant signal reg [1:0] state; // State variable always @(posedge clk) begin case (state) 2'b00: begin // State 0 - Wait for requests if (req[0] == 1) // If request 0 is asserted state <= 2'b01; // Move to state 1 else if (req[1] == 1) // If request 1 is asserted state <= 2'b10; // Move to state 2 end 2'b01: begin // State 1 - Grant request 0 grant <= 1; // Assert grant signal if (req[1] == 1) // If request 1 is asserted state <= 2'b10; // Move to state 2 else state <= 2'b00; // Move to state 0 end 2'b10: begin // State 2 - Grant request 1 grant <= 1; // Assert grant signal if (req[0] == 1) // If request 0 is asserted state <= 2'b01; // Move to state 1 else state <= 2'b00; // Move to state 0 end endcase end endmodule In this code, the three request signals (req) are input to the module along with the clock signal (clk), and the grant signal is output. The module has a state variable (state) which determines which request signal to grant. In the initial state (state=2'b00), the module waits for any of the three request signals to be asserted. If request 0 (req[0]) is asserted, the module moves to state 1 (2'b01) and grants request 0 by asserting the grant signal. If request 1 (req[1]) is asserted, the module moves to state 2 (2'b10) and grants request 1. Once a request is granted, the module checks the other two request signals to see if they are still asserted. If another request is asserted, the module moves to the corresponding state and grants that request. If no other requests are asserted, the module returns to the initial state and waits for a new request to be asserted.
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