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Verigy V93000

Seamlessly Integrated Design-to-Test (EDA) for the V93000

Throughout the semiconductor industry, test engineers spend considerable time creating unique, customized individual production test programs in an attempt to respond to the most complex and pressing design and time to market challenges. However, custom

program development is often cumbersome, slow and error prone, and lacks the availability of standardized, automated toolsets that can quickly produce and validate complete test programs and fully leverage their test system's capabilities.

For users of its V93000 test system, Verigy now offers SmarTest Data Link* - an

integrated “design-to-test” tool designed to maximize the use of the advanced features and capabilities of the V93000: X- modes, Concurrent Testing, Multiple Clock Domains, Yield Learning, and more. This fully automated solution virtually eliminates the need to create custom tooling to accomplish critical design-to-test tasks.

With SmarTest Data Link, Verigy addresses the increasing demand for rapid

development and debug of test programs, and the fast conversion of all ATPG and EDA test data languages: VCD, EVCD, WGL, STIL.

*SmarTest Data Link is based on leading edge STILlink technology from Test Insight.

STIL/WGL Translator

SmarTest Data Link for the V93000 delivers the fastest processing times for directly

translating STIL and WGL test data formats. Also included is full support for STIL signal pins timing, and levels (IEEE 1450.0-1499, 1450.1, 1450.2). SmarTest Data Link also

leading ATPG tools: Mentor Graphics Fast Scan®, Synopsys TetraMAX®, and more.

Complete translation solution integrated into Verigy’s SmarTest operating

system: Optimized support for all V93000 digital cards and test processor controlled power supplies (Ce/P, Pin Scale 400/800/3600/HX, DC Scale DPS32/VI32/UHC4); full support for x-modes (maximizing vector memory utilization), multi-port (concurrent testing), multi clock domain, and pattern synchronous DC (Vbump, Iddx); and better tester resource utilization through timing, waveforms, and levels reuse (incremental mode).

Get the most out of your V93000 with SmarTest Data Link:

Full loop back to simulation for cyclized test vectors or post processed V93000 binariesSupport for most common EDA standards

Advanced EDA and ATE

capabilities without changes to the conversion process

The full power of the V93000’s test processor-per-pin architecture-enabling per-pin-resources for digital and DC channelsIntegrated support for Verigy Yield Learning solutions and SCAN Pattern based data logging

Integrated solution for program

creation from EDA to the V93000. Pin configuration,

levels, timing and vector generation for fastest TTM and optimized tester resource utilization