顺手贴个ttl信息
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MT7621 stage1 code 10:33:11 (ASIC)
CPU=50000000 HZ BUS=16666666 HZ
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Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x11100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-1200Mhz ===
PLL2 FB_DL: 0xa, 1/0 = 593/431 29000000
PLL3 FB_DL: 0xe, 1/0 = 613/411 39000000
PLL4 FB_DL: 0x12, 1/0 = 801/223 49000000
do DDR setting..[00320381]
Apply DDR3 Setting...(use customer AC)
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
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忽略
rank 0 coarse = 15
rank 0 fine = 72
B:| 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0
opt_dle value:9
DRAMC_R0DELDLY[018]=00002121
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RX DQS perbit delay software calibration
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1.0-15 bit dq delay value
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bit| 0 1 2 3 4 5 6 7 8 9
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0 | 10 9 10 10 7 9 9 7 5 7
10 | 9 10 9 11 7 9
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2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay:DQS0 =33 DQS1 = 33
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bit DQS0 bit DQS1
忽略
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3.dq delay value last
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