1.板子采用的是黑金的AX301
2.只是依葫芦画葫芦,再加上自己的一些想法吧
3.个人觉得,在事件中学到的,比看课本要掌握的快许多
【1】新建工程
File -> New Project Wizard
-> Introduction (Next)
-> Directory,Name,Top-Level Entity[1/5] (input ur custom Info Then Next)
-> [2/5] (Add Files or Ignore Then Next)
-> [3/5] (Select Dvice Family:Cyclone IV E, Package:FBGA, Pin Count:256,Speed grade:8,Avilable device:EP4CE6F17C8)
-> [4/5] (Select Simulation:Modelsim,Verilog HDL)
-> Finish
【2】添加Verilog文件
File -> New...
->Verilog HDL File
-> OK
【3】增加代码
1 'timescale 1ns/1ps //时间尺度预编译指令,定义仿真时的时间单位和精度 2 3 module led_test(clk,rst_n,led); //led_test必须与项目同名,区别大小写。 4 //clk:开发板上的输入时钟:50MHz 5 //rest_n:开发板上的输入复位按键 6 //led:输出LED灯,用于控制开发板上的四个LED(LED0~LED3) 7 8 //=============================== 9 //Port Declaration:端口声明 10 //=============================== 11 12 input clk; //clk为输入端口 13 input rst_n; //rest_n也是输入端口 14 output [3:0] led; //led为四个输出端口 15 16 //=============================== 17 //Register Declaration:寄存器声明 18 //=============================== 19 20 reg [31:0] timer; //定义计时器寄存器 21 reg [3:0] led; //定义led,I/O口寄存器 22 23 //=============================== 24 //计数器技术:循环技术0~4s 25 //=============================== 26 27 always @(posedge clk or negedge rst_n) //begin&end:类似于C语言的花括号 28 begin 29 if(~rst_n) //复位按键按下,计时器清零 30 timer <= 0; //<=是赋值语句,而不是小于等于 31 else if(timer == 32'd199_999_999) //开发板使用的晶振为50MHz,4s计数:(50MHz*4-1=199_999_999) 32 timer <= 0; //计数器溢出清零 33 else 34 timer <= timer + 1'd1; //猜测:1'd是指1位十进制数字 35 end 36 37 //=============================== 38 //LED控制 39 //=============================== 40 41 always @(posedge clk or negedge rst_n) //监测时钟信号的上升沿或复位信号的下降沿 42 begin 43 if(~rst_n) 44 led <= 4'b0000; //复位按键按下时,全部熄灭 45 else if(timer == 32'd49_999_999) 46 led <= 4'b0001; 47 else if(timer == 32'd99_999_999) 48 led <= 4'b0010; 49 else if(timer == 32'd149_999_999) 50 led <= 4'b0100; 51 else if(timer == 32'd199_999_999) 52 led <= 4'b1000; 53 end 54 55 endmodule //模块结束
-> Save File As led_test.v
【4】管脚约束和编译
右键选中 Cyclone IV E ->Device
-> Device and Pin Options
-> Select all Pins as Use as regular I/O
-> Voltage as 3.3-v LVTTL ->OK
-> 右键单击 Compile Design ->Start
单击 Assignments -> Pin Planner
-> Select the Correct Pin Location of every Node
【5】时序约束
告诉编译器在编译时按照时序要求布线。高速信号设计尤其需要注意
点击 Tool -> TimeQuest Timing Analyzer
-> Tools ->TimeQueat Timing Analyzer Wizard
-> Intro (Next)
-> Clock (Set Clock Name as clk,input Pin as clk; period as 1/50M = 20ns,Rising as 0,Falling as 10 Then Next)
-> tsu/th (Setup Time and Holdup Time using for High Speed Circuit,Ignore Then Next)
-> tco (min and max Hold Time of Output,Ignore Then Next)
-> tpd (Next)
-> FInish
【6】编译下载
-> ReCompile
-> Coneect FPGA
-> Open Program Device
-> Hardware Setup -> Select USB_Blaster[USB-*] -> Close
-> Add File -> Select *.sof File
-> Start
※-未完待续-※