这个程序的寄存器读取时和STM32通讯的，之前有一个是和AVR通讯的，这个程序已经调试通过，原理比较简单，相信认真看的都能够明白。
因为ADS8364为差分AD，所以其输出为补码形式，按照2.5V的参考电压源输出的数据范围为-32768~+32768，如果AIN- 连到VREF(2.5V)，那么当AIN+ 输入为0时 输出的数据为0x8000，如果AIN+ 输入为2.5V则输出数据为0x0000，AIN+ 输入为5V时输出数据位0x7F。程序如下：
1 --最后修改2011.3.26 2 3 --最后测试功能： 4 5 --利用第一块板子测试ADS8364 6 7 library ieee; 8 9 use ieee.std_logic_1164.all; 10 11 use ieee.std_logic_unsigned.all; 12 13 -------------------------------------------------------------------------------------- 14 15 --此段定义系统的各信号线 16 17 -------------------------------------------------------------------------------------- 18 19 entity ad is 20 21 port( 22 23 -- 系统信号线 24 25 clk: in std_logic; 26 27 led:outstd_logic; 28 29 rst: in std_logic; 30 31 -- arm相连的信号线 32 33 adr_l: in std_logic_vector(7 downto 0); --a7...a0,只使用了低八位地址线 34 35 data: inout std_logic_vector(7 downto 0); --只使用了低八位数据线 36 37 fsmc_ne4: in std_logic; 38 39 fsmc_noe: in std_logic; 40 41 fsmc_nwe: in std_logic; 42 43 --ad8364信号线 44 45 adc_d: in std_logic_vector(15 downto 0); 46 47 adc_a0,adc_a1,adc_a2: out std_logic; 48 49 adc_reset: out std_logic; 50 51 adc_cs: out std_logic; 52 53 adc_wr: out std_logic; 54 55 adc_rd: out std_logic; 56 57 adc_holda,adc_holdb,adc_holdc:outstd_logic; 58 59 adc_eoc: in std_logic; 60 61 adcclk_out:out std_logic 62 63 64 65 ); 66 67 end entity; 68 69 70 71 --统一编址，地址线数据线为八位，每个地址数据宽度8位 72 73 --"00000001" ad0_h_data0x01 74 75 --"00000010" ad0_l_data0x02 76 77 --"00000011" ad1_h_data0x03 78 79 --"00000100" ad1_l_data0x04 80 81 --"00000101" led_ctrl0x05 82 83 84 85 architecture art of ad is 86 87 -------------------------------------------------------------------------------------- 88 89 --此段定义内部相应的寄存器和相应变量 90 91 -------------------------------------------------------------------------------------- 92 93 94 95 --stm32读写相关信号 96 97 98 99 --设置存储数据的寄存器 100 101 signal ad0_h_data,ad0_l_data,ad1_h_data,ad1_l_data,led_ctrl: std_logic_vector(7 downto 0); 102 103 --数据缓冲寄存器 104 105 signal data_buf: std_logic_vector(7 downto 0); 106 107 --数据输出控制 108 109 signal data_outctl: std_logic; 110 111 112 113 --时钟分频相关变量 114 115 signal clkcnt:std_logic_vector(16 downto 0); 116 117 signal adc_clk:std_logic;--adc时钟信号 118 119 signal adc_data_buf:std_logic_vector(15 downto 0); 120 121 122 123 --定义读取过程的各个状态 124 125 --13位控制分别为 hold adc_a rd 状态机状态5位 hhhabcr 126 127 ---------------------------------------------------98365 128 129 constant st0:std_logic_vector(11 downto 0):="000000100000";--启动转换 130 131 constant st1:std_logic_vector(11 downto 0):="111000100001";--进入17个周期等待转换结束，不检测EOC 132 133 constant st2:std_logic_vector(11 downto 0):="111000100010"; 134 135 constant st3:std_logic_vector(11 downto 0):="111000100011"; 136 137 constant st4:std_logic_vector(11 downto 0):="111000100100"; 138 139 constant st5:std_logic_vector(11 downto 0):="111000100101"; 140 141 constant st6:std_logic_vector(11 downto 0):="111000100110"; 142 143 constant st7:std_logic_vector(11 downto 0):="111000100111"; 144 145 constant st8:std_logic_vector(11 downto 0):="111000101000"; 146 147 constant st9:std_logic_vector(11 downto 0):="111000101001"; 148 149 constant st10:std_logic_vector(11 downto 0):="111000101010"; 150 151 constant st11:std_logic_vector(11 downto 0):="111000101011"; 152 153 constant st12:std_logic_vector(11 downto 0):="111000101100"; 154 155 constant st13:std_logic_vector(11 downto 0):="111000101101"; 156 157 constant st14:std_logic_vector(11 downto 0):="111000101110"; 158 159 constant st15:std_logic_vector(11 downto 0):="111000101111"; 160 161 constant st16:std_logic_vector(11 downto 0):="111000110000"; 162 163 constant st17:std_logic_vector(11 downto 0):="111000110001"; 164 165 constant st18:std_logic_vector(11 downto 0):="111000110010"; 166 167 constant st19:std_logic_vector(11 downto 0):="111000010011";--读ch1数据 168 169 constant st20:std_logic_vector(11 downto 0):="111001110100"; 170 171 constant st21:std_logic_vector(11 downto 0):="111001010101";--读ch2数据 172 173 constant st22:std_logic_vector(11 downto 0):="111001110110"; 174 175 176 177 signal state:std_logic_vector(11 downto 0);--用于状态跳转 178 179 signal readst:std_logic_vector(3 downto 0);--adc_a，在另一个进程中根据此信号 选择输出的数据 180 181 182 183 begin 184 185 ------------------------------------------------时钟分频------------------------------------------------------------------- 186 187 process(rst,clk) is 188 189 begin 190 191 if rst='0' then 192 193 clkcnt <= "00000000000000000"; 194 195 elsif(clk'event and clk = '1') then 196 197 if(clkcnt = "11111111111111111") then 198 199 clkcnt<= "00000000000000000"; 200 201 else 202 203 clkcnt <= clkcnt+1; 204 205 end if; 206 207 end if; 208 209 end process; 210 211 --pwm_clk <= clkcnt(7);--分频pwm时钟 212 213 --led_clk <= clkcnt(16);--分频led时钟 214 215 216 217 led <= clkcnt(16);--分频led时钟 218 219 adc_clk <= clkcnt(3); 220 221 adcclk_out <= clkcnt(3); 222 223 224 225 226 227 228 229 -------------------------------------------------------------------------------------- 230 231 --stm32读写程序 232 233 --根据stm32读写时序图和信号线设计，实际上并没有使用全部信号线 234 235 -------------------------------------------------------------------------------------- 236 237 238 239 --当读取cpld数据时用来判断何时向总线上输出数据 240 241 data_outctl <= (not fsmc_ne4) and (not fsmc_noe) and (fsmc_nwe); 242 243 data <= data_buf when (data_outctl='1') else "ZZZZZZZZ";--向数据线输出数据，否则保持为高阻态 244 245 246 247 -- 写操作,模式1,时序图在数据手册p331 248 249 process(rst,fsmc_ne4,fsmc_nwe,adr_l,fsmc_noe) is 250 251 begin 252 253 if rst='0' then 254 255 256 257 elsif(fsmc_nwe'event and fsmc_nwe='1') then 258 259 if((fsmc_noe and (not fsmc_ne4))='1') then 260 261 case (adr_l) is 262 263 when "00000001" =>--对应的地址 264 265 266 267 when "00000010" => 268 269 270 271 when "00000011" => 272 273 274 275 when "00000100" => 276 277 278 279 when "00000101" => 280 281 282 283 when others => 284 285 286 287 end case; 288 289 end if; 290 291 end if; 292 293 end process; 294 295 296 297 --读操作,模式1,p331 298 299 process(rst,fsmc_ne4,fsmc_nwe,adr_l,fsmc_noe) is 300 301 begin 302 303 if rst= '0' then 304 305 data_buf<="00000000"; 306 307 elsif(fsmc_noe='0' and fsmc_noe'event) then --直接在noe的下降沿更新数据 308 309 case (adr_l) is 310 311 when "00000001" => 312 313 data_buf <= ad0_h_data; --0x01 314 315 when "00000010" => 316 317 data_buf <= ad0_l_data; --0x02 318 319 when "00000011" => 320 321 data_buf <= ad1_h_data; --0x03 322 323 when "00000100" => 324 325 data_buf <= ad1_l_data; --0x04 326 327 when "00000101" => 328 329 data_buf <= "11001100"; --0x05 330 331 when others => data_buf <= "ZZZZZZZZ"; 332 333 end case; 334 335 end if; 336 337 end process; 338 339 --------------------------------------ads8364------------------------------------ 340 341 --ads8364控制，默认byte=0，add=0 342 343 adc_cs <= '0'; --片选一直选中 344 345 adc_wr <= '1'; 346 347 --ads状态转移 348 349 process(adc_clk,rst) 350 351 begin 352 353 if(rst='0') then 354 355 state<=st0; 356 357 adc_reset<='0'; 358 359 adc_holda<='1'; 360 361 adc_holdb<='1'; 362 363 adc_holdc<='1'; 364 365 elsif(adc_clk'event and adc_clk='1') then 366 367 adc_reset<='1'; 368 369 case state is 370 371 when st0=> state<=st1; 372 373 when st1=> state<=st2; 374 375 when st2=> state<=st3; 376 377 when st3=> state<=st4; 378 379 when st4=> state<=st5; 380 381 when st5=> state<=st6; 382 383 when st6=> state<=st7; 384 385 when st7=> state<=st8; 386 387 when st8=> state<=st9; 388 389 when st9=> state<=st10; 390 391 when st10=> state<=st11; 392 393 when st11=> state<=st12; 394 395 when st12=> state<=st13; 396 397 when st13=> state<=st14; 398 399 when st14=> state<=st15; 400 401 when st15=> state<=st16; 402 403 when st16=> state<=st17; 404 405 when st17=> state<=st18; 406 407 when st18=> state<=st19; 408 409 when st19=> state<=st20; 410 411 when st20=> state<=st21; 412 413 when st21=> state<=st22; 414 415 when st22=> state<=st0; 416 417 when others=> state<=st0; 418 419 end case; 420 421 end if; 422 423 readst<=state(8 downto 5); 424 425 adc_holdc<=state(11); 426 427 adc_holdb<=state(10); 428 429 adc_holda<=state(9); 430 431 adc_a2<=state(8); 432 433 adc_a1<=state(7); 434 435 adc_a0<=state(6); 436 437 adc_rd<=state(5); 438 439 end process; 440 441 442 443 process(clk,adc_d) 444 445 begin 446 447 if(clk'event and clk='0')then 448 449 adc_data_buf(14 downto 0) <= adc_d(14 downto 0); 450 451 adc_data_buf(15) <= not adc_d(15); 452 453 if readst="0000" then 454 455 ad0_h_data <= adc_data_buf(15 downto 8); 456 457 ad0_l_data <= adc_data_buf(7 downto 0); 458 459 elsif readst="0010" then 460 461 ad1_h_data <= adc_data_buf(15 downto 8); 462 463 ad1_l_data <= adc_data_buf(7 downto 0); 464 465 end if; 466 467 end if; 468 469 end process; 470 471 end; 472 473 474 475 476 477
1990
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