【随笔】Verilog HDL

1 // captrue the edge of busy and record
2   always @(posedge clk or posedge busy or negedge reset_n) begin
3 if (reset_n == 1 ' b0)
4 begin
5 busy_posedge_reg <= 1 ' b0;
6 end
7 else if (stage_reg == EDLE)
8 begin
9 busy_posedge_reg <= 1 ' b0;
10 end
11 else
12 begin
13 busy_posedge_reg <= 1 ' b1;
14 end
15 end

 

产生错误提示：

 

 

Error ( 10200 ): Verilog HDL Conditional Statement error at s1_slave.v( 176 ): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

 

 

 

 

转载于:https://www.cnblogs.com/xiyi/archive/2010/11/24/1886983.html