FPGA 关于错误（10200）

本人在调试FPGA时有时会出现以下错误：

Error (10200): Verilog HDL Conditional Statement error at delay.v(23): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

问题原因在于笔者用了以下语句
always@(posedge clk or negedge rst_n)
却粗心的忘了对rst_n进行判断了写成如下语句了

always@(posedge clk or negedge rst_n)
begin 
 if(txd_flag)
    if(state < 4'd9)
           state<=state+1;
    else
          state<=0;
 else 
            state<=state;
end

而正确的应该是

always@(posedge clk or negedge rst_n)
begin 
 if(!rst_n)
        begin
            state<=0;
        end
 else if(txd_flag)
    if(state < 4'd9)
           state<=state+1;
    else
          state<=0;
 else 
            state<=state;
end