1065 A+B and C (64bit) (20 分)

1065 A+B and C (64bit) (20 分)

Given three integers A, B and C in [2^63​​,2​^63​​], you are supposed to tell whether A+B>C.

Input Specification:

The first line of the input gives the positive number of test cases, T (10). Then T test cases follow, each consists of a single line containing three integers A, B and C, separated by single spaces.

Output Specification:

For each test case, output in one line Case #X: true if A+B>C, or Case #X: false otherwise, where X is the case number (starting from 1).

Sample Input:

3
1 2 3
2 3 4
9223372036854775807 -9223372036854775808 0

Sample Output:

Case #1: false
Case #2: true
Case #3: false


分析:这个题有坑点,涉及到计算机组成原理的知识,数字的范围是[2^63​​,2​^63​​], 而long long 的范围是[-2^63,2^63),两个数相加会溢出,符号位会取反。
 1 /**
 2 * Copyright(c)
 3 * All rights reserved.
 4 * Author : Mered1th
 5 * Date : 2019-02-23-19.49.08
 6 * Description : A1065
 7 */
 8 #include<cstdio>
 9 #include<cstring>
10 #include<iostream>
11 #include<cmath>
12 #include<algorithm>
13 #include<string>
14 #include<unordered_set>
15 #include<map>
16 #include<vector>
17 #include<set>
18 using namespace std;
19 
20 int main(){
21 #ifdef ONLINE_JUDGE
22 #else
23     freopen("1.txt", "r", stdin);
24 #endif
25     int n,num=1;
26     scanf("%d",&n);
27     for(int i=1;i<=n;i++){
28         long long a,b,c;
29         scanf("%lld%lld%lld",&a,&b,&c);
30         bool flag;
31         long long res=a+b;
32         if(a>0&&b>0&&res<0) flag=true;
33         else if(a<0&&b<0&&res>=0) flag=false;
34         else if(res>c) flag=true;
35         else flag=false;
36         if(flag==true) printf("Case #%d: true\n",i);
37         else printf("Case #%d: false\n",i);
38     }
39 
40     return 0;
41 }

 

转载于:https://www.cnblogs.com/Mered1th/p/10424044.html

好的,我可以为您提供一个简单的Verilog代码和Testbench来实现这个8位7功能算术逻辑部件。代码如下: ``` module alu( input [7:0] A, input [7:0] B, input Ci, input [2:0] op, output reg [7:0] D, output reg CF, output reg ZF ); reg [3:0] A_add, B_add; reg [4:0] A_sub, B_sub; reg [7:0] A_and, A_or, A_xor, A_nor; assign A_add = {1'b0, A}; assign B_add = {1'b0, B}; assign A_sub = {1'b0, ~A, 1'b1}; assign B_sub = {1'b0, B}; assign A_and = A & B; assign A_or = A | B; assign A_xor = A ^ B; assign A_nor = ~(A | B); always @(*) begin case (op) 3'b000: D = A_add + B_add + Ci; 3'b001: D = A_add + B_sub + Ci; 3'b010: D = A_add + B_add + Ci; 3'b011: D = A_add + B_sub - Ci; 3'b100: D = A_and; 3'b101: D = A_or; 3'b110: D = A_xor; 3'b111: D = A_nor; endcase CF = D[8]; ZF = (D == 0); end endmodule ``` Testbench模块: ``` module alu_tb; reg [7:0] A; reg [7:0] B; reg Ci; reg [2:0] op; wire [7:0] D; wire CF; wire ZF; alu dut( .A(A), .B(B), .Ci(Ci), .op(op), .D(D), .CF(CF), .ZF(ZF) ); initial begin $dumpfile("alu_tb.vcd"); $dumpvars(0, alu_tb); #1; // 功能控制: 000:A + B; 001:A – B; 010:A + B + Ci; 011:A - B - Ci; 100:A & B; 101:A # B; 110:A @ B; 111:A @ B; A = 8'b01010101; B = 8'b10101010; Ci = 0; op = 3'b000; #1; if (D !== 8'b00000000 || CF !== 1'b1 || ZF !== 1'b0) begin $display("ADD, ERROR"); end else begin $display("ADD, OK"); end op = 3'b001; #1; if (D !== 8'b11111111 || CF !== 1'b0 || ZF !== 1'b0) begin $display("SUB, ERROR"); end else begin $display("SUB, OK"); end op = 3'b010; Ci = 1; #1; if (D !== 8'b00000000 || CF !== 1'b1 || ZF !== 1'b0) begin $display("ADC, ERROR"); end else begin $display("ADC, OK"); end op = 3'b011; Ci = 1; #1; if (D !== 8'b11111111 || CF !== 1'b0 || ZF !== 1'b0) begin $display("SBC, ERROR"); end else begin $display("SBC, OK"); end op = 3'b100; #1; if (D !== 8'b00000000 || CF !== 1'b0 || ZF !== 1'b1) begin $display("AND, ERROR"); end else begin $display("AND, OK"); end op = 3'b101; #1; if (D !== 8'b11111111 || CF !== 1'b0 || ZF !== 1'b0) begin $display("OR, ERROR"); end else begin $display("OR, OK"); end op = 3'b110; #1; if (D !== 8'b11111111 || CF !== 1'b0 || ZF !== 1'b0) begin $display("XOR, ERROR"); end else begin $display("XOR, OK"); end op = 3'b111; #1; if (D !== 8'b00000000 || CF !== 1'b0 || ZF !== 1'b0) begin $display("NOR, ERROR"); end else begin $display("NOR, OK"); end #10; $finish; end endmodule ``` 在这个Testbench中我们进行了所有功能的测试,并通过比较输出结果和预期结果来判断是否正确。如果正确,输出“功能名称, OK”,否则输出“功能名称, ERROR”。其中,CF表示进位标识位,ZF表示零标识位。 希望这个代码能够帮到您,如果还有其他问题,请随时提出。
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