verilog behavioral modeling--overview

1.verilog behavioral models contain procedural statements that control the simulation and manipulate variables of the data types.These statements are concurrent to model the inherent concurrence of hardware.

2.all of the flows defined by the initial and always constructs start together at simulation time zero.The initial constructs execute once,and the always constructs execute repetitively.

eg:

   module behave;

      reg [1:0] a,b;

      initial begin

          a='b1;

          b='b0;

      end

    always begin

        #50 a = ~a;

    end

   always begin

       #100 b=~b;

  end

  endmodule

 

转载于:https://www.cnblogs.com/chip/p/4071993.html