在加入了时序约束文件vip_top.sdc就正常了,以下是vip_top.sdc的内容:
1
#
**************************************************************
2 # Time Information
3 # **************************************************************
4
5
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7 set_time_format - unit ns - decimal_places 3
8
9 # **************************************************************
10 # Create Clock
11 # **************************************************************
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13 create_clock - name {clk125_in} - period 8.000 - waveform { 0.000 4.000 } [get_ports {clk125_in}]
14 #create_clock - name {BITEC_QV_CH1_IN_CLK} - period 37.000 - waveform { 0.000 18.500 } [get_ports {BITEC_QV_CH1_IN_CLK}]
2 # Time Information
3 # **************************************************************
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7 set_time_format - unit ns - decimal_places 3
8
9 # **************************************************************
10 # Create Clock
11 # **************************************************************
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13 create_clock - name {clk125_in} - period 8.000 - waveform { 0.000 4.000 } [get_ports {clk125_in}]
14 #create_clock - name {BITEC_QV_CH1_IN_CLK} - period 37.000 - waveform { 0.000 18.500 } [get_ports {BITEC_QV_CH1_IN_CLK}]