aSRAM IS61LV25626仿真模型(原厂模型基础上增加了记录文件功能)

SRAM_IS61LV25616的仿真模型(原厂模型基础上增加了读写记录文件功能)

  1 // IS61LV25616 Asynchronous SRAM, 256K x 16 = 4M; speed: 10ns.
  2 // Note; 1) Please include "+define+ OEb" in running script if you want to check
  3 //          timing in the case of OE_ being set.
  4 //       2) Please specify access time by defining tAC_10 or tAC_12.
  5 `define Debug     //使能后将输出sram读写记录文件
  6 `define OEb
  7 `define tAC_10     //tAC_10 or tAC_12 defines different parameters
  8 `timescale 1ns/1ns
  9 
 10 module IS61LV25616 (A, IO, CE_, OE_, WE_, LB_, UB_);
 11 
 12 parameter dqbits = 16;
 13 parameter memdepth = 262143;
 14 parameter addbits = 19;
 15 parameter Toha  = 2;
 16 
 17 parameter Tsa   = 2;
 18 
 19 `ifdef tAC_10         //if "`define tAC_10 " at beginning,sentences below are compiled
 20   parameter Taa   = 10,
 21             Thzce = 3,
 22           Thzwe = 5;
 23 `endif
 24 
 25 `ifdef tAC_12        //if "`define tAC_12 " at beginning,sentences below are compiled
 26   parameter Taa   = 12,
 27           Thzce = 5,
 28           Thzwe = 6;
 29 `endif
 30 
 31 input CE_, OE_, WE_, LB_, UB_;
 32 input [(addbits - 1) : 0] A;
 33 inout [(dqbits - 1) : 0] IO;
 34  
 35 wire [(dqbits - 1) : 0] dout;
 36 reg  [(dqbits/2 - 1) : 0] bank0 [0 : memdepth];  
 37 reg  [(dqbits/2 - 1) : 0] bank1 [0 : memdepth];
 38 //array to simulate SRAM
 39 // wire [(dqbits - 1) : 0] memprobe = {bank1[A], bank0[A]};
 40 
 41 wire r_en = WE_ & (~CE_) & (~OE_);   //WE=1,CE=OE=0 Read
 42 wire w_en = (~WE_) & (~CE_) & ((~LB_) | (~UB_)); //WE=CE=0,LB or UB="0",OE=x Write
 43 assign #(r_en ? Taa : Thzce) IO = r_en ? dout : 16'bz;      // 读数据时，经过Taa的延时，内部数据输出到IO端口
 44                                                             // 不读时(写)，IO口保持输出，Thzce时间后才变成高阻输入
 45 
 46 initial
 47   $timeformat (-9, 0.1, " ns", 10); //show current simulation time
 48 
 49 assign dout [(dqbits/2 - 1) : 0]        = LB_ ? 8'bz : bank0[A];
 50 assign dout [(dqbits - 1) : (dqbits/2)] = UB_ ? 8'bz : bank1[A];
 51 
 52 always @(A or w_en)
 53   begin
 54     #Tsa    //address setup time
 55     if (w_en)
 56       #Thzwe
 57       begin
 58  bank0[A] = LB_ ? bank0[A] : IO [(dqbits/2 - 1) : 0];  //写数据时，IO口的数据经过(Tsa+Thzwe)才写入内部ram
 59  bank1[A] = UB_ ? bank1[A] : IO [(dqbits - 1)   : (dqbits/2)];
 60 
 61       end
 62   end
 63  
 64 // Timing Check
 65 `ifdef tAC_10
 66   specify        //sepcify delay
 67     specparam
 68       tSA   = 0,
 69       tAW   = 8,
 70       tSCE  = 8,
 71       tSD   = 6,
 72       tPWE2 = 10,
 73       tPWE1 = 8,
 74       tPBW  = 8;
 75 `else
 76 
 77 `ifdef tAC_12
 78   specify
 79     specparam
 80       tSA   = 0,
 81       tAW   = 8,
 82       tSCE  = 8,
 83       tSD   = 6,
 84       tPWE2 = 12,
 85       tPWE1 = 8,
 86       tPBW  = 8;
 87 `endif
 88 `endif
 89 
 90     $setup (A, negedge CE_, tSA);
 91     $setup (A, posedge CE_, tAW);
 92     $setup (IO, posedge CE_, tSD);
 93     $setup (A, negedge WE_, tSA);
 94     $setup (IO, posedge WE_, tSD);
 95     $setup (A, negedge LB_, tSA);
 96     $setup (A, negedge UB_, tSA);
 97 
 98     $width (negedge CE_, tSCE);
 99     $width (negedge LB_, tPBW);
100     $width (negedge UB_, tPBW);
101     `ifdef OEb
102     $width (negedge WE_, tPWE1);
103     `else
104     $width (negedge WE_, tPWE2);
105     `endif
106 
107   endspecify
108 
109   
110   
111   // 读数据时，经过Taa的延时，内部数据输出到IO端口
112 // 不读时(写)，IO口保持输出，Thzce时间后才变成高阻输入
113 // 写数据时，IO口的数据经过(Tsa+Thzwe)才写入内部ram  
114       `ifdef Debug
115         begin        
116             integer fp;    
117             
118             initial
119                 begin
120                     fp = $fopen("SRAM Write Record.log")    ;
121                     $fdisplay(fp,"====SRAM Write Record ====");    
122                 end
123                 
124             always @(A or w_en)
125                 begin
126                     #Tsa    //address setup time
127                     if (w_en)
128                     #Thzwe    
129                     $fdisplay(fp,"%t/t,%m: Sram Write OK: Adder=%d, Data= %d ",$time, A, IO);
130                 end
131                 
132             always@(posedge r_en)
133                 begin
134                     #Taa
135                     $fdisplay(fp,"%t/t,%m: Sram Read OK: Adder=%d, Data= %d ",$time, A, IO);
136                 end
137     `endif
138 endmodule

转载于:https://www.cnblogs.com/fishplj2000/archive/2012/03/30/2424937.html