MK64FN1M0xxx12_flash.ld链接文件解析

1.前言

本文主要对MK64FN1M0xxx12_flash.ld文件进行分析,以此来加深对链接文件的理解

2.文件详解

/*
** ###################################################################
**     Processors:          MK64FN1M0CAJ12
**                          MK64FN1M0VDC12
**                          MK64FN1M0VLL12
**                          MK64FN1M0VLQ12
**                          MK64FN1M0VMD12
**
**     Compiler:            GNU C Compiler
**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
**     Version:             rev. 2.9, 2016-03-21
**     Build:               b170817
**
**     Abstract:
**         Linker file for the GNU C Compiler
**
**     Copyright 2016 Freescale Semiconductor, Inc.
**     Copyright 2016-2017 NXP
**     Redistribution and use in source and binary forms, with or without modification,
**     are permitted provided that the following conditions are met:
**
**     1. Redistributions of source code must retain the above copyright notice, this list
**       of conditions and the following disclaimer.
**
**     2. Redistributions in binary form must reproduce the above copyright notice, this
**       list of conditions and the following disclaimer in the documentation and/or
**       other materials provided with the distribution.
**
**     3. Neither the name of the copyright holder nor the names of its
**       contributors may be used to endorse or promote products derived from this
**       software without specific prior written permission.
**
**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
**     http:                 www.nxp.com
**     mail:                 support@nxp.com
**
** ###################################################################
*/

/* Entry Point */
NOTE:程序中第一条运行的指令被称为入口点entry point,可以使用ENTRY链接脚本命令设置entry point,参数是一个符号名:

有几种方法可以设置entry point,链接器会按照如下的顺序来try各种方法,只要任何一种方法成功则会停止:
  • the ‘-e’ entry command-line option;
  • the ENTRY(symbol) command in a linker script;
  • the value of the symbol start, if defined;
  • the address of the first byte of the ‘.text’ section, if present;
  • The address 0
ENTRY(Reset_Handler)
/*
DEFINED(symbol)用于判断symbol在符号表中是否有定义,如果有定义则返回1否则返回0
*/ 
HEAP_SIZE
= DEFINED(__heap_size__) ? __heap_size__ : 0x0400; STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; /* Specify the memory areas */

/*定义内存区域的起始地址和长度*/ MEMORY { m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010 m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0 m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000 } /* Define output sections */ SECTIONS { /* The startup code goes first into internal flash */ .interrupts : { . = ALIGN(4);
/*
isr_vector在start.S中定义:.section .isr_vector, "a",按照MEMORY命令说明,isr_vector由于没有指定输出section,因此会创建与输入section同名的输出section,且会按照
isr_vector的属性放到合适的内存区域,此处KEEP是保证isr_vector的输出section不会被删除
*/
    KEEP(*(.isr_vector))     /* Startup code */
    . = ALIGN(4);
  } > m_interrupts

  .flash_config :
  {
    . = ALIGN(4);
    KEEP(*(.FlashConfig))    /* Flash Configuration Field (FCF) */
    . = ALIGN(4);
  } > m_flash_config

  /* The program code and other data goes into internal flash */
  .text :
  {
    . = ALIGN(4);
    *(.text)                 /* .text sections (code) */
    *(.text*)                /* .text* sections (code) */
    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
    *(.glue_7)               /* glue arm to thumb code */
    *(.glue_7t)              /* glue thumb to arm code */
    *(.eh_frame)
    KEEP (*(.init))
    KEEP (*(.fini))
    . = ALIGN(4);
  } > m_text

  .ARM.extab :
  {
    *(.ARM.extab* .gnu.linkonce.armextab.*)
  } > m_text

  .ARM :
  {
    __exidx_start = .;
    *(.ARM.exidx*)
    __exidx_end = .;
  } > m_text

 .ctors :
  {
    __CTOR_LIST__ = .;
    /* gcc uses crtbegin.o to find the start of
       the constructors, so we make sure it is
       first.  Because this is a wildcard, it
       doesn't matter if the user does not
       actually link against crtbegin.o; the
       linker won't look for a file to match a
       wildcard.  The wildcard also means that it
       doesn't matter which directory crtbegin.o
       is in.  */
    KEEP (*crtbegin.o(.ctors))
    KEEP (*crtbegin?.o(.ctors))
    /* We don't want to include the .ctor section from
       from the crtend.o file until after the sorted ctors.
       The .ctor section from the crtend file contains the
       end of ctors marker and it must be last */
    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
    KEEP (*(SORT(.ctors.*)))
    KEEP (*(.ctors))
    __CTOR_END__ = .;
  } > m_text

  .dtors :
  {
    __DTOR_LIST__ = .;
    KEEP (*crtbegin.o(.dtors))
    KEEP (*crtbegin?.o(.dtors))
    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
    KEEP (*(SORT(.dtors.*)))
    KEEP (*(.dtors))
    __DTOR_END__ = .;
  } > m_text

  .preinit_array :
  {
    PROVIDE_HIDDEN (__preinit_array_start = .);
    KEEP (*(.preinit_array*))
    PROVIDE_HIDDEN (__preinit_array_end = .);
  } > m_text

  .init_array :
  {
    PROVIDE_HIDDEN (__init_array_start = .);
    KEEP (*(SORT(.init_array.*)))
    KEEP (*(.init_array*))
    PROVIDE_HIDDEN (__init_array_end = .);
  } > m_text

  .fini_array :
  {
    PROVIDE_HIDDEN (__fini_array_start = .);
    KEEP (*(SORT(.fini_array.*)))
    KEEP (*(.fini_array*))
    PROVIDE_HIDDEN (__fini_array_end = .);
  } > m_text

  __etext = .;    /* define a global symbol at end of code */
  __DATA_ROM = .; /* Symbol is used by startup for data initialization */

  .data : AT(__DATA_ROM)
  {
    . = ALIGN(4);
    __DATA_RAM = .;
    __data_start__ = .;      /* create a global symbol at data start */
    *(.data)                 /* .data sections */
    *(.data*)                /* .data* sections */
    KEEP(*(.jcr*))
    . = ALIGN(4);
    __data_end__ = .;        /* define a global symbol at data end */
  } > m_data

  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
  text_end = ORIGIN(m_text) + LENGTH(m_text);
  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")

  /* Uninitialized data section */
  .bss :
  {
    /* This is used by the startup in order to initialize the .bss section */
    . = ALIGN(4);
    __START_BSS = .;
    __bss_start__ = .;
    *(.bss)
    *(.bss*)
    *(COMMON)
    . = ALIGN(4);
    __bss_end__ = .;
    __END_BSS = .;
  } > m_data

  .heap :
  {
    . = ALIGN(8);
    __end__ = .;
    PROVIDE(end = .);
    __HeapBase = .;
    . += HEAP_SIZE;
    __HeapLimit = .;
    __heap_limit = .; /* Add for _sbrk */
  } > m_data_2

  .stack :
  {
    . = ALIGN(8);
    . += STACK_SIZE;
  } > m_data_2

  /* Initializes stack on the end of block */
  __StackTop   = ORIGIN(m_data_2) + LENGTH(m_data_2);
  __StackLimit = __StackTop - STACK_SIZE;
  PROVIDE(__stack = __StackTop);

  .ARM.attributes 0 : { *(.ARM.attributes) }

  ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
}

 

转载于:https://www.cnblogs.com/smartjourneys/p/8194251.html

  • 0
    点赞
  • 0
    收藏
    觉得还不错? 一键收藏
  • 0
    评论
这些文件是 Verilator 工程目录中的一些典型文件,它们的作用如下: - `Vtop`:这是由 Verilator 生成的仿真器可执行文件。它是通过编译 Verilog 或 SystemVerilog 源代码生成的 C++ 代码构建的。 - `Vtop__ALL.a`:这是一个静态链库,包含了仿真器的所有对象文件,用于构建仿真器可执行文件。 - `Vtop__Syms.cpp`:这是由 Verilator 自动生成的 C++ 源文件,包含了仿真器中使用到的模块和信号的符号表信息。 - `Vtop___024root__Slow.cpp`:这是由 Verilator 自动生成的 C++ 源文件,包含了仿真器中的主时钟生成逻辑。 - `Vtop.cpp`:这是由 Verilator 自动生成的 C++ 源文件,包含了仿真器的主要逻辑,包括初始化、仿真循环等。 - `Vtop__Syms.h`:这是由 Verilator 自动生成的头文件,包含了仿真器中使用到的模块和信号的符号表定义。 - `Vtop__ver.d`:这是由 Verilator 自动生成的依赖文件,记录了仿真器构建过程中所依赖的源文件。 - `sim_main.d`:这是由编译过程中生成的依赖文件,记录了仿真器构建过程中所依赖的其他文件。 - `sim_main.o`:这是由编译器生成的目标文件,包含了仿真器构建过程中编译的源文件的对象代码。 - `Vtop.h`:这是由 Verilator 自动生成的头文件,包含了仿真器中模块和信号的定义。 - `Vtop__ALL.cpp`:这是由 Verilator 自动生成的 C++ 源文件,包含了仿真器中所有对象的构造和析构函数。 - `Vtop___024root.cpp`:这是由 Verilator 自动生成的 C++ 源文件,包含了仿真器中主时钟生成逻辑的实现。 - `Vtop__verFiles.dat`:这是由 Verilator 自动生成的文件列表,记录了仿真器构建过程中所使用到的源文件。 - `verilated.d`:这是由 Verilator 自动生成的依赖文件,记录了仿真器构建过程中所依赖的其他文件。 - `verilated.o`:这是由编译器生成的目标文件,包含了仿真器构建过程中编译的 Verilator 的相关代码的对象代码。 这些文件是 Verilator 工具在编译和构建过程中生成的中间和输出文件,用于生成仿真器可执行文件,并提供仿真所需的功能和口。
评论
添加红包

请填写红包祝福语或标题

红包个数最小为10个

红包金额最低5元

当前余额3.43前往充值 >
需支付:10.00
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明:

1.余额是钱包充值的虚拟货币,按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载,可以购买VIP、付费专栏及课程。

余额充值