Computer Organization and Design--计组作业习题（3）

Computer Organization and Design

 

  ----------------------个人作业，如果有后辈的作业习题一致，可以参考学习，一起交流，请勿直接copy

Problem 1: Floating Point Arithmetic (5 points)

 

Assume that we are using the IEEE 754 32-bit floating point format for this question.

(a) Convert the decimal number 8.34375 to floating point representation

 

 0  10000010  0001 0110 0000 0000 0000 000

 

(b) Convert the floating point number 0100 0000 1001 1000 0000 0000 0000 0000 to decimal

 

 4.75

 

(c) Perform floating point addition by adding the result from part (a) to the floating point number given in part (b).  Show the floating point representation that would be used in hardware.

 

 13.09375

 0  10000010  1010 0010 0000 0000 0000 000

 

 

Problem 2: Timing Diagram (5 points)

The circuit below consists of a D flip-flop and an OR gate.  Complete the timing diagram below for signals Y and Z.

 

 

 

 

Problem 3: Finite State Machine Design (7 points)

You have been assigned the task of designing a finite state machine containing one input (X) and one output (Z).  Your machine will get a pseudo-randomly selected bit as input X every cycle (so every time there is a positive clock edge, a new bit X will be fed into your FSM).  Your machine should assert Z (set to 1) when the last three bits taken in as input match the sequence “101”, setting Z to 0 in all other situations.  For example, your machine should never assert Z after receiving a sequence of “1001”, but Z should be asserted after receiving the final “1” in a sequence like “01101”.  Draw the FSM diagram below.  Full credit will be given for machines containing six or less states.

 

 由题意得，下表为状态表：

 

S S/X X	0	1
S0	S0/0	S1/0
S1	S2/0	S1/0
S2	S0/0	S3/0
S3	S2/0	S1/0

 

 

 下表为相对应的编码表：

 

X	Q1	~Q1	Q0	~Q0	Z
0	0	0	0	0	0
0	0	1	1	0	0
0	1	0	0	0	0
1	0	0	0	1	0
1	0	0	1	1	0
1	1	0	0	1	1

 

 则，由上表可得知如下状态转移图：

 

    

   图示为：X/Z

Problem 4: Single Cycle Datapath (10 points)

(a)Assume the following delays for an LC-2K single-cycle datapath

• Memory read/write: 10ns

• Register file read/write: 3ns

• ALU operations: 5ns

• All other components have negligible delay

 

 

We assume a benchmark with the following distribution of instructions: 20% add, 30% lw, 30% beq, 20% sw.  Determine the execution times for one instance of each of the 4 instructions listed, and then identify the minimum clock cycle for this benchmark.

 

 Add：10+3+5+3=21ns

 Lw： 10+3+5+10+3=31ns

 Beq：10+3+5=18ns

 Sw： 10+3+5+10=28ns

 

 Minimum clock cycle : 31ns

 

(b)You are asked to alter the current LC-2K processor described in class to accommodate a new instruction.  This instruction is called zero_copy and the pseudocode for it is as follows:

 

if (regB == 0)

　　regB = regA;

else

　　regB = 0;

 

In this instruction, the opcode is stored in bits 24-22, regA is stored in bits 21-19, regB is stored in bits 18-16, and bits 15-0 are unused.

What extra hardware(s) do you need to add in order for this instruction to function correctly?  Hardware may include wires, mux’s, etc.  On the next page is a copy of the LC-2K processor.  You may use this for reference and draw in the hardware necessary to implement this instruction.  Please draw your implementation neatly and label all additions clearly.  If your solution is difficult to read it will not be graded.

 

 

如图所示，1 0 1 X X 0 X

Problem 5: Multicycle Datapath (3 points)

Consider the multicycle LC-2K architecture from class.  Assume we have a benchmark to run that contains 500 instructions.  These instructions consist of

• 30% lw

• 30% sw

• 15% beq

• 25% add

 

 

(a) How many cycles are needed to complete this benchmark?

 

 

 Total cycles:  500*30%*5+500*(30%+25%+15%)*4=2150 

 

 

 

(b) What is the CPI for this benchmark?

 

 

  CPI cycles:  2150/500=4.3 

 

(c) Given that the clock period for the multicycle architecture is 10ns, what is the total execution time for this benchmark?

 

 Total execution time:  2150*10=21500 ns

转载于:https://www.cnblogs.com/nanashi/p/6661650.html