Computer Organization and Design--计组作业习题（7）

 

Computer Organization and Design

 

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Problem 1 (VM Design) (8 points)

 

You are given a system with the following specifications:

 

32 bit virtual address space

4 GB of physical memory

1 KB pages

4 B page table entry

 

a) How many virtual pages are there?

 

 

virtual pages：2³²/2¹⁰ = 2²² ；

 

 

b) How many addressable physical pages are there?

 

 

physical pages：2³²/2¹⁰ = 2²² ；

 

 

 

c) Consider the following additional information:

Design: 3-level page table. All tables except the last level table must fit exactly in a single page each.

Each page table entry must be byte aligned, and needs to store 1 valid bit + address. 

 

i) How much memory would the entire page table take for the design above?

 

 

 

a)  1 KB (= 1 page). => 2^10/5 = 204, 2^7 page table entries

b)  2^7 x 1 KB=> 2^7x2^7 = 2^14 page table entries

c)  2^14 x 2^22/2^14 page table entries => 2^14 x 2^8 x 2^2 B

 

Total size = 1 KB + 1 KB x 2^7 + 2^14 x 2^8 x 2^2 B = 16909312 bytes

     

 

 

ii) Can you partition the address bits differently, but still keeping the 3-level page table design, such that the amount of memory required to store the entire page table is the minimum possible? (Any level of page table must not take more memory than a single page). Show your work.

 

 

 

a)   6 bits => 2^6 x 2^2 B

b)   8 bits => 2^6 x 1 KB (=>(2^6 x 2^10/2^2 = 2^14 page table entries)

c)   8 bits => 2^14 x 1 KB => 2^24 B

 

Total size = 2^8 + 2^16 + 2^24 B = 16843008 bytes

 

 

Problem 2 (VM in action) (9 points)

 

Consider the following computer with a CPU, data cache and memory:

● The system has a 16-bit virtual address size, and the size of a virtual memory page is 4 KB. The computer has 64 KB of physical memory.

● The size of the CPU data cache is 1 KB, with a block size of 16 bytes. The CPU data cache is 4-way set associative with LRU replacement, and it is a virtually indexed cache. 

● The CPU includes a fully associative TLB with 8 entries and a LRU replacement policy. The system uses a single level page table. 

 

 

Assume the TLB and the data cache are initially empty. The contents of the page table are shown below:

 

 

VPN	Valid	PPN
0x0	1	0x1
0x1	1	0xa
0x2	0	-
0x3	1	0x0
0x4	1	0x8
0x5	1	0xb
0x6	0	-
0x7	0	-
0x8	1	0x3
0x9	1	0x5
0xa	1	0x6
0xb	1	0xc
0xc	0	-
0xd	1	0xf
0xe	0	-
0xf	0	-

 

 

Data reads from the following virtual addresses are performed in the order listed:

0x002f, 0x1020, 0xfba8, 0xae26, 0xcf2a, 0xdbaf, 0xae2f, 0xfca1, 0x102b

Please complete the following table to show the following for each read:

● Physical address (in hex)

● Data cache hit/miss (write H or M)

● TLB hit/miss (write H or M, or NA is TLB is not accessed)

 

 

 

Virtual Address	Physical Address	Data Cache Hit/Miss	TLB Hit/Miss/NA
0x002f	0x102f	M	M
0x1020	0xa020	M	M
0xfba8	------	M	M
0xae26	0x6e26	M	M
0xcf2a	------	M	M
0xdbaf	0xfbaf	M	M
0xae2f	0x6e2f	H	NA
0xfca1	------	M	M
0x102b	0xa02b	H	NA

 

 

Problem 3 (VM Performance) (2 points)

 

Given the following information: 

● TLB hit rate: 99 %, TLB access time is 1 cycle

● Cache hit rate: 92 %, cache access time is 1 cycle

● Page fault rate: 0.5 % of memory accesses

● The TLB access and cache access are sequential

● Accesses to main memory require 100 cycles

● Accesses to the hard drive require 100,000 cycles

 

 

Compute the average memory access latency.

 

 Average memory access latency :

 

 (1-92%)*(1 + 99%*100 + (1-99%)*(100 + (1-0.5%)*100 + 0.5%*100000)) +1= 9.5596 cycles

 

 

转载于:https://www.cnblogs.com/nanashi/p/6662285.html