西南交大计算机组成实验C(VHDL)-实验五 CPU寄存器组设计
西南交大计算机组成实验C(VHDL)-实验五 CPU寄存器组设计
西南交大计算机组成实验C-E5
实验目的,实验目的,说明实验仪器、设备等说明参见《计算机组成实验C》实验及课程设计指导书
程序代码
CPU寄存器组设计:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CPU is
port(CLK,Wr,Rd,RESET:in std_logic;--WR,RD,写/读控制,低电平有效
RA,M:in std_logic_vector(1 downto 0);--RA1 RA0控制4个通用寄存器 M1 M0控制PC寄存器四种操作
D: in std_logic_vector(7 downto 0);--置数操作
SEL:buffer std_logic_vector(2 downto 0);
LED7:out std_logic_vector(7 downto 0)
);
end entity CPU;
architecture one of CPU is
shared variable R0,R1,R2,R3,PC,temp:std_logic_vector(7 downto 0);
signal DATA:std_logic_vector(3 downto 0);
signal SEL_temp:std_logic_vector(2 downto 0);
signal times:std_logic_vector(7 downto 0);
begin
process(CLK,RESET,M)
begin
if CLK'event and CLK='0' then
times<=times+1;
if RESET='0' then PC:="00000000";
else -- RESET ='1'
if times ="0" then
case M is
when "00" =>PC:=D(7 downto 0);
when "01" =>PC:=PC+1;
when "10" =>PC:=PC-1;
when others=>null;
end case;
end if;
end if;
end if;
end process;
process(RA,Wr,Rd)
begin
case RA is
when "00" => if Wr='0' and Rd='1' then R0:=D(7 downto 0);
elsif Wr='1' and Rd='0' then temp:=R0;--temp读取寄存器数据
end if;
when "01" => if Wr='0' and Rd='1' then R1:=D(7 downto 0);
elsif Wr='1' and Rd='0' then temp:=R1;--temp读取寄存器数据
end if;
when "10" => if Wr='0' and Rd='1' then R2:=D(7 downto 0);
elsif Wr='1' and Rd='0' then temp:=R2;--temp读取寄存器数据
end if;
when "11" => if Wr='0' and Rd='1' then R3:=D(7 downto 0);
elsif Wr='1' and Rd='0' then temp:=R3;--temp读取寄存器数据
end if;
when others => null;
end case;
end process;
process(CLK)
begin
if CLK'event and CLK='1' then
SEL_temp<=SEL_temp+1;
if SEL_temp>="011" then SEL_temp<="000";end if;
SEL<=SEL_temp;
case SEL_temp is
when "000"=>DATA<=temp(7 downto 4);
when "001"=>DATA<=temp(3 downto 0);
when "010"=>DATA<=PC(7 downto 4);
when "011"=>DATA<=PC(3 downto 0);
when others=>NULL;
end case;
end if;
end process;
process(DATA)
begin
case DATA is
WHEN "0000"=> LED7<="00111111";--0
WHEN "0001"=> LED7<="00000110";--1
WHEN "0010"=> LED7<="01011011";--2
WHEN "0011"=> LED7<="01001111";--3
WHEN "0100"=> LED7<="01100110";--4
WHEN "0101"=> LED7<="01101101";--5
WHEN "0110"=> LED7<="01111101";--6
WHEN "0111"=> LED7<="00000111";--7
WHEN "1000"=> LED7<="01111111";--8
WHEN "1001"=> LED7<="01101111";--9
WHEN "1010"=> LED7<="01110111";--10
WHEN "1011"=> LED7<="01111100";--11
WHEN "1100"=> LED7<="00111001";--12
WHEN "1101"=> LED7<="01011110";--13
WHEN "1110"=> LED7<="01111001";--14
WHEN "1111"=> LED7<="01110001";--15
WHEN OTHERS =>NULL;
end case;
end process;
end architecture one;连线参考图:
引脚锁定参考:
引脚锁定可能并不符合读者使用习惯,仅供参考。
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