我遇到的警告错误及解决方法

 

可以不用理会的：

 Warning: Found 11 output pins without output pin load capacitance assignment

警告原因：没有指定IO口负载电容，可以不理会

 

 

需要解决的：

Warning: Latch audio_deal:audio_deal_inst|val_vrefl[2] has unsafe behavior     Warning: Ports D and ENA on the latch are fed by the same signal audio_deal:audio_deal_inst|waveform_l[0]

解决： if...else...要写全

 

Warning: An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It's required that the timescale should be 1 ps when simulating a PLL design in a third party EDA tool.

解决：要将仿真时间改为1ps，但奇怪的是我的工程中都没有用到PLL却有这样的提示。

 

转载于:https://www.cnblogs.com/sungngaichen/p/3760361.html