/***********************************************
函 数: main
功 能: 程序入口
输 入: /
输 出: /
描 述: /
***********************************************/
void main(void)
{
u8 i,length;
delay_ms(1000);
CLOCK_init();//时钟8分频 2M RC
delay_ms(200);
InitializeSystem();
if(POWER_KEY==0)
{
POWER_EN6=1;
POWER_EN5=0;
}
else
{
POWER_EN6=0;
POWER_EN5=1;
}
LED_BIT=1;
//enableInterrupts(); //开总中断
Get_ADC(4);//进行ADC转换，获得AD值
delay_ms(100);
SetTimer2(50000);
disableInterrupts();
WakeUpFlag=1;
while( 1 )
{
if(! SI4463_IRQ_BIT)
{
SI446X_INT_STATUS( SI4463_Buf );
if( SI4463_Buf[3] & ( 1<<4 ) )
{
// Get RSSI
SI446X_RSSI_INFO(&Rssi_Value);
//收到一个数据包，翻转LED
length = SI446X_READ_PACKET( SI4463_Buf );
if(modbus_cmd( SI4463_Buf , RW_Reg_Req_Len )==0)//检查功能码并计算校验
{
if((SI4463_Buf[1] == XIUGAI_433M_ID)&&(!POWER_KEY))
{
LED_BIT=0;
RxOverTime=0;
WaitCnt=0;
SI4463_Txd[1]=XIUGAI_433M_ID;
LocationID[0]=SI4463_Buf[11];
LocationID[1]=SI4463_Buf[12];
LocationID[2]=SI4463_Buf[13];
LocationID[3]=SI4463_Buf[14];
EEPROM_Write(0x4002,LocationID[0]);
EEPROM_Write(0x4003,LocationID[1]);
EEPROM_Write(0x4004,LocationID[2]);
EEPROM_Write(0x4005,LocationID[3]);
RW_MultiReg_Ack(SI4463_Txd[1], LocationID[0] ,LocationID[1], LocationID[2], LocationID[3]); //发送轮询命令
while(SI4463_IRQ_BIT);
SI446X_INT_STATUS( SI4463_Buf );
}
if( (SI4463_Buf[1] == XIUGAI_433M_MAC)&&(!POWER_KEY))
{
LED_BIT=0;
RxOverTime=0;
WaitCnt=0;
SI4463_Txd[1]=XIUGAI_433M_MAC;
LocationMac[0]=SI4463_Buf[11];
LocationMac[1]=SI4463_Buf[12];
LocationMac[2]=SI4463_Buf[13];
LocationMac[3]=SI4463_Buf[14];
EEPROM_Write(0x4008,LocationMac[0]);
EEPROM_Write(0x4009,LocationMac[1]);
EEPROM_Write(0x400a,LocationMac[2]);
EEPROM_Write(0x400b,LocationMac[3]);
RW_MultiReg_Ack(SI4463_Txd[1], LocationMac[0] ,LocationMac[1], LocationMac[2], LocationMac[3]); //发送轮询命令
while(SI4463_IRQ_BIT);
SI446X_INT_STATUS( SI4463_Buf );
}
if( (SI4463_Buf[1] == SET_433M_RF_POWER)&&(!POWER_KEY))
{
LED_BIT=0;
RxOverTime=0;
WaitCnt=0;
SI4463_Txd[1]=SET_433M_RF_POWER;
RF_PA_POWER_SET[5]=SI4463_Buf[18];
EEPROM_Write(0x400c,RF_PA_POWER_SET[5]);//保存功率设置
SI446X_CMD( RF_PA_POWER_SET, 8 ); //发射功率设置
RW_MultiReg_Ack(SI4463_Txd[1], RF_PA_POWER_SET[5] ,LocationMac[1], LocationMac[2], LocationMac[3]); //发送轮询命令
while(SI4463_IRQ_BIT);
SI446X_INT_STATUS( SI4463_Buf );
}
if( (SI4463_Buf[1] == SCAN_433M_ID)&&(SI4463_Buf[11]==LocationID[0]) )
{
LED_BIT=0;
RxOverTime=0;
WaitCnt=0;
RW_MultiReg_Ack(SI4463_Txd[1], LocationID[0] ,LocationID[1], LocationID[2], LocationID[3]); //发送轮询命令
while(SI4463_IRQ_BIT);
SI446X_INT_STATUS( SI4463_Buf );
}
if( (SI4463_Buf[1] == MAC_SCAN_433M)&&(SI4463_Buf[11]==LocationID[0]))
//if( SI4463_Buf[1] == MAC_SCAN_433M)
{
LED_BIT=0;
RxOverTime=0;//接收超时时间清0
WaitCnt=0;//休眠时间清0
SI4463_Txd[1]=MAC_SCAN_433M;
RW_MultiReg_Ack(SI4463_Txd[1], LocationMac[0] ,LocationMac[1], LocationMac[2], LocationMac[3]); //发送轮询命令
while(SI4463_IRQ_BIT);
SI446X_INT_STATUS( SI4463_Buf );
WakeUpFlag=0;
}
if( (SI4463_Buf[1] == VERSION_SCAN_433M)&&(SI4463_Buf[11]==LocationMac[0]) )//版本号命令
{
LED_BIT=0;
RxOverTime=0;
WaitCnt=0;
SI4463_Txd[1]=VERSION_SCAN_433M;
RW_Version_Ack(SI4463_Txd[1], LocationMac[0] ,LocationMac[1], LocationMac[2], LocationMac[3],LocationVersion); //发送轮询命令
while(SI4463_IRQ_BIT);
SI446X_INT_STATUS( SI4463_Buf );
}
//回到接收模式，继续等待信号
SI446X_START_RX( 0, 0, PACKET_LENGTH,0,3,3 );
Get_ADC(4);//进行ADC转换，获得AD值
}
} //end if( buffer[3] & ( 1<<4 ) )
SI446X_START_RX( 0, 0, PACKET_LENGTH,0,3,3 );
if( !WakeUpFlag )
{
WakeUpFlag=1;
WaitCnt=0;
RxOverTime=0;
SI_SDN_HIGH();//关闭射频SI4463模块，进入低功耗
WakeUpState=0;//模块休眠状态
}
} //end if((PD_IDR&0x04)==0x00)
if(ELECTRIC_BIT)
{
ElectricValue=0xff;//市电接入
}
else
ElectricValue=0x0a; //市电断开
if(TIM2_SR1&0x01)
{
TIM2_SR1=0x00;//清除第一次无效中断
RxOverTime++;
WaitCnt++;
}
if((WaitCnt>140)&&(!WakeUpState) )//7.5S唤醒
{
WaitCnt=0;
WakeUpFlag=1;
SI446X_RESET(); //SI446X 模块复位
SI446X_CONFIG_INIT(); //SI446X 模块初始化配置函数
SI446X_START_RX( 0, 0, PACKET_LENGTH,0,3,3 );
WakeUpState=1;//模块唤醒状态
}
if(RxOverTime>260)//超过13S没有收到轮询，主动发送 一条
{
RxOverTime=0;
SI446X_RESET(); //SI446X 模块复位
SI446X_CONFIG_INIT(); //SI446X 模块初始化配置函数
SI446X_START_RX( 0, 0, PACKET_LENGTH,0,3,3 );
SI4463_Txd[1]=MAC_SCAN_433M;
RW_MultiReg_Ack(SI4463_Txd[1], LocationMac[0] ,LocationMac[1], LocationMac[2], LocationMac[3]); //发送轮询命令
while(SI4463_IRQ_BIT);
SI446X_INT_STATUS( SI4463_Buf );
WaitCnt=0;
RxOverTime=0;
SI446X_INT_STATUS( SI4463_Buf );
SI446X_START_RX( 0, 0, PACKET_LENGTH,0,3,3 );
}
LED_BIT=1;
} //end while(1)
} //end main
/******************************************************************************************************************/
/*****************系统初始化*****************************/
void InitializeSystem()
{
sbi(POWER_EN6_DDR,6);//电源使能-直接EN 输出
sbi(POWER_EN6_CR1,6);
cbi(POWER_EN6_CR2,6);
sbi(POWER_EN5_DDR,5);//电源使能脚PNP 输出
sbi(POWER_EN5_CR1,5);
cbi(POWER_EN5_CR2,5);
POWER_EN6=1;
POWER_EN5=0;
sbi(LED_DDR,3);//LED控制脚PC3 输出
sbi(LED_CR1,3);
cbi(LED_CR2,3);
LED_BIT=0;
cbi(POWER_KEY_DDR,4);//开机按键PD4 输入
sbi(POWER_KEY_CR1,4);
cbi(POWER_KEY_CR2,4);
cbi(ELECTRIC_DDR,4);//市电状态PC4 输入
sbi(ELECTRIC_CR1,4);
cbi(ELECTRIC_CR2,4);
cbi(SI4463_IRQ_DDR,2);//SI4463中断脚 输入
sbi(SI4463_IRQ_CR1,2);
cbi(SI4463_IRQ_CR2,2);
#if 0
LocationID[0]=EEPROM_Write(0x4002,1);
LocationMac[0]=EEPROM_Write(0x4008,0x66);
#endif
#if 1
LocationID[0]=EEPROM_Read(0x4002);
LocationID[1]=EEPROM_Read(0x4003);
LocationID[2]=EEPROM_Read(0x4004);
LocationID[3]=EEPROM_Read(0x4005);
LocationMac[0]=EEPROM_Read(0x4008);
LocationMac[1]=EEPROM_Read(0x4009);
LocationMac[2]=EEPROM_Read(0x400a);
LocationMac[3]=EEPROM_Read(0x400b);
RF_PA_POWER_SET[5]=EEPROM_Read(0x400c);//读取发射功率设 置
#endif
SI4463_InterFace();
SI446X_RESET(); //SI446X 模块复位
SI446X_CONFIG_INIT(); //SI446X 模块初始化配置函数
SI446X_START_RX( 0, 0, PACKET_LENGTH,0,3,3 );
}
/******************************************************************************************************************/
void SI446X_INT_STATUS( INT8U *buffer )
{
INT8U cmd[4];
cmd[0] = GET_INT_STATUS;
cmd[1] = 0;
cmd[2] = 0;
cmd[3] = 0;
SI446X_CMD( cmd, 4 );
SI446X_READ_RESPONSE( buffer, 9 );
}
/******************************************************************************************************************/
void SI446X_RSSI_INFO( INT8U *buffer )
{
INT8U cmd = 0X53;//0x53快速访问寄存器C
SI446X_WAIT_CTS( );
SI_CSN_LOW( );//片选脚
SPI_ExchangeByte( cmd );//传送一个字节
*buffer = SPI_ExchangeByte( 0xFF );//读取一个字节
SI_CSN_HIGH( );
}
/******************************************************************************************************************/
void SI446X_WAIT_CTS( void )
{
INT8U cts;
do
{
SI_CSN_LOW( );
SPI_ExchangeByte( READ_CMD_BUFF );
cts = SPI_ExchangeByte( 0xFF );
SI_CSN_HIGH( );
}while( cts != 0xFF );
}
/******************************************************************************************************************/
void SI446X_CMD( INT8U *cmd, INT8U cmdsize )
{
SI446X_WAIT_CTS( );
SI_CSN_LOW( );
while( cmdsize -- )
{
SPI_ExchangeByte( *cmd++ );
}
SI_CSN_HIGH( );
}
/******************************************************************************************************************/
INT8U SPI_ExchangeByte( INT8U input )
{
u8 data;
while(!(SPI_SR & 0x02));
SPI_DR=input;
while(!(SPI_SR & 0x01));
data=SPI_DR;
return data;
}
/******************************************************************************************************************/
INT8U SI446X_READ_PACKET( INT8U *buffer )
{
INT8U length, i;
SI446X_WAIT_CTS( );
SI_CSN_LOW( );
SPI_ExchangeByte( READ_RX_FIFO );
#if PACKET_LENGTH == 0
length = SPI_ExchangeByte( 0xFF );
#else
length = PACKET_LENGTH;
#endif
i = length;
while( length -- )
{
*buffer++ = SPI_ExchangeByte( 0xFF );
}
SI_CSN_HIGH( );
return i;
}
/***********************************************发送一包数据*******************************************************************/
void SI446X_SEND_PACKET( INT8U *txbuffer, INT8U size, INT8U channel, INT8U condition )
{
INT8U cmd[5];
INT8U tx_len = size;
SI446X_TX_FIFO_RESET( );
SI_CSN_LOW( );
SPI_ExchangeByte( WRITE_TX_FIFO );
#if PACKET_LENGTH == 0
tx_len ++;
SPI_ExchangeByte( size );
#endif
while( size -- ) { SPI_ExchangeByte( *txbuffer++ ); }
SI_CSN_HIGH( );
cmd[0] = START_TX;
cmd[1] = channel;
cmd[2] = condition;
cmd[3] = 0;
cmd[4] = tx_len;
SI446X_CMD( cmd, 5 );
while((PD_IDR&0x04)==0x04);
SI_CSN_HIGH();
cmd[0] = CHANGE_STATE;
cmd[1] = 0x03;
SI446X_CMD( cmd, 2 );
}
/********************************************读中断寄存器状态**************************************************/
void SI446X_INT_STATUS( INT8U *buffer )
{
INT8U cmd[4];
cmd[0] = GET_INT_STATUS;
cmd[1] = 0;
cmd[2] = 0;
cmd[3] = 0;
SI446X_CMD( cmd, 4 );
SI446X_READ_RESPONSE( buffer, 9 );
}
/******************************************************************************************************************/
void SI446X_START_RX( INT8U channel, INT8U condition, INT16U rx_len,
INT8U n_state1, INT8U n_state2, INT8U n_state3 )
{
INT8U cmd[8];
SI446X_RX_FIFO_RESET( );
SI446X_TX_FIFO_RESET( );
cmd[0] = START_RX;
cmd[1] = channel;
cmd[2] = condition;
cmd[3] = rx_len>>8;
cmd[4] = rx_len;
cmd[5] = n_state1;
cmd[6] = n_state2;
cmd[7] = n_state3;
SI446X_CMD( cmd, 8 );
}
/************************************************清缓存******************************************************************/
void SI446X_RX_FIFO_RESET( void )
{
INT8U cmd[2];
cmd[0] = FIFO_INFO;
cmd[1] = 0x02;
SI446X_CMD( cmd, 2 );
}
/*
=================================================================================
*/
void SI446X_TX_FIFO_RESET( void )
{
INT8U cmd[2];
cmd[0] = FIFO_INFO;
cmd[1] = 0x01;
SI446X_CMD( cmd, 2 );
}
/******************************************************************************************************************/
void SI4463_InterFace(void)
{
//init io pin
sbi(PA_DDR,3);//SCS OUTPUT
sbi(PA_CR1,3);
cbi(PA_CR2,3);
sbi(PC_DDR,5);//SCK OUTPUT
sbi(PC_CR1,5);
cbi(PC_CR2,5);
sbi(PC_DDR,6);//MOSI OUTPUT
sbi(PC_CR1,6);
cbi(PC_CR2,6);
cbi(PC_DDR,7);//MISO INPUT
sbi(PC_CR1,7);
cbi(PC_CR2,7);
sbi(PA_DDR,2);//GIO1 WTR INPUT
sbi(PA_CR1,2);
cbi(PA_CR2,2);
cbi(PA_DDR,1);//GIO0 WTR INPUT
sbi(PA_CR1,1);
sbi(PA_CR2,1);
SPI_Init();
}
/******************************************************************************************************************/
void SPI_Init(void)
{
SPI_CR1|=0x04; //配置为主设备
//SPI_CR2|=0xc0; //选择单线双向数据模式（输出模式）
SPI_CR2|=0x03; //配置NSS脚为1
SPI_CR1|=0x40; //开启SPI
}
/******************************************************************************************************************/
void SI446X_CONFIG_INIT( void )
{
INT8U i;
INT16U j = 0;
INT8U abApi_Write[8];
while( ( i = config_table[j] ) != 0 )
{
j += 1;
SI446X_CMD( config_table + j, i );
j += i;
}
//
SI446X_CMD( RF_PA_POWER_SET, 8 );//重新设置发射功率
#if PACKET_LENGTH > 0 //fixed packet length
SI446X_SET_PROPERTY_1( PKT_FIELD_1_LENGTH_7_0, PACKET_LENGTH );
SI446X_SET_PROPERTY_1( PKT_FIELD_1_CRC_CONFIG, 0xA2 );
SI446X_SET_PROPERTY_1( PKT_CRC_CONFIG, 0x05 );
#else //variable packet length
SI446X_SET_PROPERTY_1( PKT_CONFIG1, 0x00 );
SI446X_SET_PROPERTY_1( PKT_CRC_CONFIG, 0x00 );
SI446X_SET_PROPERTY_1( PKT_LEN_FIELD_SOURCE, 0x01 );
SI446X_SET_PROPERTY_1( PKT_LEN, 0x2A );
SI446X_SET_PROPERTY_1( PKT_LEN_ADJUST, 0x00 );
SI446X_SET_PROPERTY_1( PKT_FIELD_1_LENGTH_12_8, 0x00 );
SI446X_SET_PROPERTY_1( PKT_FIELD_1_LENGTH_7_0, 0x01 );
SI446X_SET_PROPERTY_1( PKT_FIELD_1_CONFIG, 0x00 );
SI446X_SET_PROPERTY_1( PKT_FIELD_1_CRC_CONFIG, 0x00 );
SI446X_SET_PROPERTY_1( PKT_FIELD_2_LENGTH_12_8, 0x00 );
SI446X_SET_PROPERTY_1( PKT_FIELD_2_LENGTH_7_0, 0x10 );
SI446X_SET_PROPERTY_1( PKT_FIELD_2_CONFIG, 0x00 );
SI446X_SET_PROPERTY_1( PKT_FIELD_2_CRC_CONFIG, 0x00 );
#endif //PACKET_LENGTH
//重要： 4463的GDO2，GDO3控制射频开关， 0X20 ,0X21
//发射时必须： GDO2=1，GDO3=0
//接收时必须： GDO2=0，GDO3=1
SI446X_GPIO_CONFIG( 0, 0, 0x20, 0x21, 0, 0, 0 );//重要
}
/******************************************************************************************************************/
void SI446X_SET_PROPERTY_1( SI446X_PROPERTY GROUP_NUM, INT8U proirity )
{
INT8U cmd[5];
cmd[0] = SET_PROPERTY;
cmd[1] = GROUP_NUM>>8;
cmd[2] = 1;
cmd[3] = GROUP_NUM;
cmd[4] = proirity;
SI446X_CMD( cmd, 5 );
}
/******************************************************************************************************************/
void SI446X_GPIO_CONFIG( INT8U G0, INT8U G1, INT8U G2, INT8U G3,
INT8U IRQ, INT8U SDO, INT8U GEN_CONFIG )
{
INT8U cmd[10];
cmd[0] = GPIO_PIN_CFG;
cmd[1] = G0;
cmd[2] = G1;
cmd[3] = G2;
cmd[4] = G3;
cmd[5] = IRQ;
cmd[6] = SDO;
cmd[7] = GEN_CONFIG;
SI446X_CMD( cmd, 8 );
SI446X_READ_RESPONSE( cmd, 8 );
}
/******************************************************************************************************************/
void SI446X_READ_RESPONSE( INT8U *buffer, INT8U size )
{
SI446X_WAIT_CTS( );
SI_CSN_LOW( );
SPI_ExchangeByte( READ_CMD_BUFF );//0X44
while( size -- )
{
*buffer++ = SPI_ExchangeByte( 0xFF );
}
SI_CSN_HIGH( );
}
/******************************************************************************************************************/
寄存器相关定义和命令宏
/******************************************************************************************************************/
#ifndef _SI446X_DEFS_H_
#define _SI446X_DEFS_H_
// commands for SI446x
typedef enum
{
/*BOOT COMMANDS-------------------------------------*/
POWER_UP = 0x02, // Power up
/*COMMON COMMANDS-----------------------------------*/
NOP = 0x00, //No operation command.
PART_INFO = 0x01, //Reports basic information about the device.
FUNC_INFO = 0x10, //Returns the Function revision information of the device.
GET_INT_STATUS = 0x20, //Returns the interrupt status of ALL the possible interrupt events
//(both STATUS and PENDING). Optionally, it may be used to
//clear latched (PENDING) interrupt events.
SET_PROPERTY = 0x11, //Sets the value of a property.
GET_PROPERTY = 0x12, //Retrieve a property's value.
FIFO_INFO = 0x15, //Provides access to transmit and receive FIFO counts and reset.
GPIO_PIN_CFG = 0x13, //Configures the gpio pins.
CHANGE_STATE = 0x34, //Update state machine entries.
REQUEST_DEVICE_STATE = 0x33, //Request current device state.
READ_CMD_BUFF = 0x44, //Used to read CTS and the command response.
FRR_A_READ = 0x50, //Reads the fast response registers starting with A.
FRR_B_READ = 0x51, //Reads the fast response registers starting with B.
FRR_C_READ = 0x53, //Reads the fast response registers starting with C.
FRR_D_READ = 0x57, //Reads the fast response registers starting with D.
/*IR_CAL_COMMANDS----------------------------------*/
IRCAL = 0x17, //Image rejection calibration.
/*TX_COMMANDS--------------------------------------*/
START_TX = 0x31, //Switches to TX state and starts packet transmission.
WRITE_TX_FIFO = 0x66, //Writes the TX FIFO.
/*RX_COMMANDS--------------------------------------*/
GET_MODEM_STATUS = 0x22, //Returns the interrupt status of the Modem Interrupt Group
//(both STATUS and PENDING). Optionally, it may be used
//to clear latched (PENDING) interrupt events.
PACKET_INFO = 0x16, //Returns information about the last packet received and
//optionally overrides field length.
START_RX = 0x32, //Switches to RX state. Command arguments are retained though
//sleep state, so these only need to be written when they change.
RX_HOP = 0x36, //Hop to a new frequency while in RX.
READ_RX_FIFO = 0x77, //READ_RX_FIFO
/*ADVANCED_COMMANDS-------------------------------*/
GET_PH_STATUS = 0x21, //Returns the interrupt status of the Packet Handler Interrupt
//Group (both STATUS and PENDING). Optionally, it may be used
//to clear latched (PENDING) interrupt events.
GET_CHIP_STATUS = 0x23, //Returns the interrupt status of the Chip Interrupt Group
//(both STATUS and PENDING). Optionally, it may be used to
//clear latched (PENDING) interrupt events.
PROTOCOL_CFG = 0x18, //Sets the chip up for specified protocol.
GET_ADC_READING = 0x14 //Performs and retrieve the results of possible ADC conversions.
}SI446X_CMD_X;
// priority for SI446x
typedef enum
{
GLOBAL_XO_TUNE = 0x0000,
GLOBAL_CLK_CFG = 0x0001,
GLOBAL_LOW_BATT_THRESH = 0x0001,
GLOBAL_CONFIG = 0x0003,
GLOBAL_WUT_CONFIG = 0x0004,
GLOBAL_WUT_M_15_8 = 0x0005,
GLOBAL_WUT_M_7_0 = 0x0006,
GLOBAL_WUT_R = 0x0007,
GLOBAL_WUT_LDC = 0x0008,
GLOBAL_WUT_CAL = 0x0009,
INT_CTL_ENABLE = 0x0100,
INT_CTL_PH_ENABLE = 0x0101,
INT_CTL_MODEM_ENABLE = 0x0102,
INT_CTL_CHIP_ENABLE = 0x0103,
FRR_CTL_A_MODE = 0x0200,
FRR_CTL_B_MODE = 0x0201,
FRR_CTL_C_MODE = 0x0202,
FRR_CTL_D_MODE = 0x0203,
PREAMBLE_TX_LENGTH = 0x1000,
PREAMBLE_CONFIG_STD_1 = 0x1001,
PREAMBLE_CONFIG_NSTD = 0x1002,
PREAMBLE_CONFIG_STD_2 = 0x1003,
PREAMBLE_CONFIG = 0x1004,
PREAMBLE_PATTERN_31_24 = 0x1005,
PREAMBLE_PATTERN_23_16 = 0x1006,
PREAMBLE_PATTERN_15_8 = 0x1007,
PREAMBLE_PATTERN_7_0 = 0x1008,
PREAMBLE_POSTAMBLE_CONFIG = 0x1009,
PREAMBLE_POSTAMBLE_PATTERN_31_24 = 0x100A,
PREAMBLE_POSTAMBLE_PATTERN_23_16 = 0x100B,
PREAMBLE_POSTAMBLE_PATTERN_15_8 = 0x100C,
PREAMBLE_POSTAMBLE_PATTERN_7_0 = 0x100D,
SYNC_CONFIG = 0x1100,
SYNC_BITS_31_24 = 0x1101,
SYNC_BITS_23_16 = 0x1102,
SYNC_BITS_15_8 = 0x1103,
SYNC_BITS_7_0 = 0x1104,
PKT_CRC_CONFIG = 0x1200,
PKT_CONFIG1 = 0x1206,
PKT_LEN = 0x1208,
PKT_LEN_FIELD_SOURCE = 0x1209,
PKT_LEN_ADJUST = 0x120A,
PKT_TX_THRESHOLD = 0x120B,
PKT_RX_THRESHOLD = 0x120C,
PKT_FIELD_1_LENGTH_12_8 = 0x120D,
PKT_FIELD_1_LENGTH_7_0 = 0x120E,
PKT_FIELD_1_CONFIG = 0x120F,
PKT_FIELD_1_CRC_CONFIG = 0x1210,
PKT_FIELD_2_LENGTH_12_8 = 0x1211,
PKT_FIELD_2_LENGTH_7_0 = 0x1212,
PKT_FIELD_2_CONFIG = 0x1213,
PKT_FIELD_2_CRC_CONFIG = 0x1214,
PKT_FIELD_3_LENGTH_12_8 = 0x1215,
PKT_FIELD_3_LENGTH_7_0 = 0x1216,
PKT_FIELD_3_CONFIG = 0x1217,
PKT_FIELD_3_CRC_CONFIG = 0x1218,
PKT_FIELD_4_LENGTH_12_8 = 0x1219,
PKT_FIELD_4_LENGTH_7_0 = 0x121A,
PKT_FIELD_4_CONFIG = 0x121B,
PKT_FIELD_4_CRC_CONFIG = 0x121C,
PKT_FIELD_5_LENGTH_12_8 = 0x121D,
PKT_FIELD_5_LENGTH_7_0 = 0x121E,
PKT_FIELD_5_CONFIG = 0x121F,
PKT_FIELD_5_CRC_CONFIG = 0x1220,
PKT_RX_FIELD_1_LENGTH_12_8 = 0x1221,
PKT_RX_FIELD_1_LENGTH_7_0 = 0x1222,
PKT_RX_FIELD_1_CONFIG = 0x1223,
PKT_RX_FIELD_1_CRC_CONFIG = 0x1224,
PKT_RX_FIELD_2_LENGTH_12_8 = 0x1225,
PKT_RX_FIELD_2_LENGTH_7_0 = 0x1226,
PKT_RX_FIELD_2_CONFIG = 0x1227,
PKT_RX_FIELD_2_CRC_CONFIG = 0x1228,
PKT_RX_FIELD_3_LENGTH_12_8 = 0x1229,
PKT_RX_FIELD_3_LENGTH_7_0 = 0x122A,
PKT_RX_FIELD_3_CONFIG = 0x122B,
PKT_RX_FIELD_3_CRC_CONFIG = 0x122C,
PKT_RX_FIELD_4_LENGTH_12_8 = 0x122D,
PKT_RX_FIELD_4_LENGTH_7_0 = 0x122E,
PKT_RX_FIELD_4_CONFIG = 0x122F,
PKT_RX_FIELD_4_CRC_CONFIG = 0x1230,
PKT_RX_FIELD_5_LENGTH_12_8 = 0x1231,
PKT_RX_FIELD_5_LENGTH_7_0 = 0x1232,
PKT_RX_FIELD_5_CONFIG = 0x1233,
PKT_RX_FIELD_5_CRC_CONFIG = 0x1234,
MODEM_MOD_TYPE = 0x2000,
MODEM_MAP_CONTROL = 0x2001,
MODEM_DATA_RATE_2 = 0x2003,
MODEM_DATA_RATE_1 = 0x2004,
MODEM_DATA_RATE_0 = 0x2005,
MODEM_TX_NCO_MODE_3 = 0x2006,
MODEM_TX_NCO_MODE_2 = 0x2007,
MODEM_TX_NCO_MODE_1 = 0x2008,
MODEM_TX_NCO_MODE_0 = 0x2009,
MODEM_FREQ_DEV_2 = 0x200A,
MODEM_FREQ_DEV_1 = 0x200B,
MODEM_FREQ_DEV_0 = 0x200C,
MODEM_FREQ_OFFSET_1 = 0x200D,
MODEM_FREQ_OFFSET_0 = 0x200E,
MODEM_TX_FILTER_COEFF_8 = 0x200F,
MODEM_TX_FILTER_COEFF_7 = 0x2010,
MODEM_TX_FILTER_COEFF_6 = 0x2011,
MODEM_TX_FILTER_COEFF_5 = 0x2012,
MODEM_TX_FILTER_COEFF_4 = 0x2013,
MODEM_TX_FILTER_COEFF_3 = 0x2014,
MODEM_TX_FILTER_COEFF_2 = 0x2015,
MODEM_TX_FILTER_COEFF_1 = 0x2016,
MODEM_TX_FILTER_COEFF_0 = 0x2017,
MODEM_TX_RAMP_DELAY = 0x2018,
MODEM_MDM_CTRL = 0x2019,
MODEM_IF_CONTROL = 0x201A,
MODEM_IF_FREQ_2 = 0x201B,
MODEM_IF_FREQ_1 = 0x201C,
MODEM_IF_FREQ_0 = 0x201D,
MODEM_DECIMATION_CFG1 = 0x201E,
MODEM_DECIMATION_CFG0 = 0x201F,
MODEM_BCR_OSR_1 = 0x2022,
MODEM_BCR_OSR_0 = 0x2023,
MODEM_BCR_NCO_OFFSET_2 = 0x2024,
MODEM_BCR_NCO_OFFSET_1 = 0x2025,
MODEM_BCR_NCO_OFFSET_0 = 0x2026,
MODEM_BCR_GAIN_1 = 0x2027,
MODEM_BCR_GAIN_0 = 0x2028,
MODEM_BCR_GEAR = 0x2029,
MODEM_BCR_MISC1 = 0x202A,
MODEM_BCR_MISC0 = 0x202B,
MODEM_AFC_GEAR = 0x202C,
MODEM_AFC_WAIT = 0x202D,
MODEM_AFC_GAIN_1 = 0x202E,
MODEM_AFC_GAIN_0 = 0x202F,
MODEM_AFC_LIMITER_1 = 0x2030,
MODEM_AFC_LIMITER_0 = 0x2031,
MODEM_AFC_MISC = 0x2032,
MODEM_AFC_ZIFOFF = 0x2033,
MODEM_ADC_CTRL = 0x2034,
MODEM_AGC_WINDOW_SIZE = 0x2038,
MODEM_AGC_RFPD_DECAY = 0x2039,
MODEM_AGC_IFPD_DECAY = 0x203A,
MODEM_FSK4_GAIN1 = 0x203B,
MODEM_FSK4_GAIN0 = 0x203C,
MODEM_FSK4_TH1 = 0x203D,
MODEM_FSK4_TH0 = 0x203E,
MODEM_FSK4_MAP = 0x203F,
MODEM_OOK_PDTC = 0x2040,
MODEM_OOK_BLOPK = 0x2041,
MODEM_OOK_CNT1 = 0x2042,
MODEM_OOK_MISC = 0x2043,
MODEM_RAW_SEARCH = 0x2044,
MODEM_RAW_CONTROL = 0x2045,
MODEM_RAW_EYE_1 = 0x2046,
MODEM_RAW_EYE_0 = 0x2047,
MODEM_ANT_DIV_MODE = 0x2048,
MODEM_ANT_DIV_CONTROL = 0x2049,
MODEM_RSSI_THRESH = 0x204A,
MODEM_RSSI_JUMP_THRESH = 0x204B,
MODEM_RSSI_CONTROL = 0x204C,
MODEM_RSSI_CONTROL2 = 0x204D,
MODEM_RSSI_COMP = 0x204E,
MODEM_CLKGEN_BAND = 0x2051,
MODEM_CHFLT_RX1_CHFLT_COE13_7_0 = 0x2100,
MODEM_CHFLT_RX1_CHFLT_COE12_7_0 = 0x2101,
MODEM_CHFLT_RX1_CHFLT_COE11_7_0 = 0x2102,
MODEM_CHFLT_RX1_CHFLT_COE10_7_0 = 0x2103,
MODEM_CHFLT_RX1_CHFLT_COE9_7_0 = 0x2104,
MODEM_CHFLT_RX1_CHFLT_COE8_7_0 = 0x2105,
MODEM_CHFLT_RX1_CHFLT_COE7_7_0 = 0x2106,
MODEM_CHFLT_RX1_CHFLT_COE6_7_0 = 0x2107,
MODEM_CHFLT_RX1_CHFLT_COE5_7_0 = 0x2108,
MODEM_CHFLT_RX1_CHFLT_COE4_7_0 = 0x2109,
MODEM_CHFLT_RX1_CHFLT_COE3_7_0 = 0x210A,
MODEM_CHFLT_RX1_CHFLT_COE2_7_0 = 0x210B,
MODEM_CHFLT_RX1_CHFLT_COE1_7_0 = 0x210C,
MODEM_CHFLT_RX1_CHFLT_COE0_7_0 = 0x210D,
MODEM_CHFLT_RX1_CHFLT_COEM0 = 0x210E,
MODEM_CHFLT_RX1_CHFLT_COEM1 = 0x210F,
MODEM_CHFLT_RX1_CHFLT_COEM2 = 0x2110,
MODEM_CHFLT_RX1_CHFLT_COEM3 = 0x2111,
MODEM_CHFLT_RX2_CHFLT_COE13_7_0 = 0x2112,
MODEM_CHFLT_RX2_CHFLT_COE12_7_0 = 0x2113,
MODEM_CHFLT_RX2_CHFLT_COE11_7_0 = 0x2114,
MODEM_CHFLT_RX2_CHFLT_COE10_7_0 = 0x2115,
MODEM_CHFLT_RX2_CHFLT_COE9_7_0 = 0x2116,
MODEM_CHFLT_RX2_CHFLT_COE8_7_0 = 0x2117,
MODEM_CHFLT_RX2_CHFLT_COE7_7_0 = 0x2118,
MODEM_CHFLT_RX2_CHFLT_COE6_7_0 = 0x2119,
MODEM_CHFLT_RX2_CHFLT_COE5_7_0 = 0x211A,
MODEM_CHFLT_RX2_CHFLT_COE4_7_0 = 0x211B,
MODEM_CHFLT_RX2_CHFLT_COE3_7_0 = 0x211C,
MODEM_CHFLT_RX2_CHFLT_COE2_7_0 = 0x211D,
MODEM_CHFLT_RX2_CHFLT_COE1_7_0 = 0x211E,
MODEM_CHFLT_RX2_CHFLT_COE0_7_0 = 0x211F,
MODEM_CHFLT_RX2_CHFLT_COEM0 = 0x2120,
MODEM_CHFLT_RX2_CHFLT_COEM1 = 0x2121,
MODEM_CHFLT_RX2_CHFLT_COEM2 = 0x2122,
MODEM_CHFLT_RX2_CHFLT_COEM3 = 0x2123,
PA_MODE = 0x2200,
PA_PWR_LVL = 0x2201,
PA_BIAS_CLKDUTY = 0x2202,
PA_TC = 0x2203,
PA_RAMP_EX = 0x2204,
PA_RAMP_DOWN_DELAY = 0x2205,
SYNTH_PFDCP_CPFF = 0x2300,
SYNTH_PFDCP_CPINT = 0x2301,
SYNTH_VCO_KV = 0x2302,
SYNTH_LPFILT3 = 0x2303,
SYNTH_LPFILT2 = 0x2304,
SYNTH_LPFILT1 = 0x2305,
SYNTH_LPFILT0 = 0x2306,
SYNTH_VCO_KVCAL = 0x2307,
MATCH_VALUE_1 = 0x3000,
MATCH_MASK_1 = 0x3001,
MATCH_CTRL_1 = 0x3002,
MATCH_VALUE_2 = 0x3003,
MATCH_MASK_2 = 0x3004,
MATCH_CTRL_2 = 0x3005,
MATCH_VALUE_3 = 0x3006,
MATCH_MASK_3 = 0x3007,
MATCH_CTRL_3 = 0x3008,
MATCH_VALUE_4 = 0x3009,
MATCH_MASK_4 = 0x300A,
MATCH_CTRL_4 = 0x300B,
FREQ_CONTROL_INTE = 0x4000,
FREQ_CONTROL_FRAC_2 = 0x4001,
FREQ_CONTROL_FRAC_1 = 0x4002,
FREQ_CONTROL_FRAC_0 = 0x4003,
FREQ_CONTROL_CHANNEL_STEP_SIZE_1 = 0x4004,
FREQ_CONTROL_CHANNEL_STEP_SIZE_0 = 0x4005,
FREQ_CONTROL_W_SIZE = 0x4006,
FREQ_CONTROL_VCOCNT_RX_ADJ = 0x4007,
RX_HOP_CONTROL = 0x5000,
RX_HOP_TABLE_SIZE = 0x5001,
RX_HOP_TABLE_ENTRY_0 = 0x5002,
RX_HOP_TABLE_ENTRY_1 = 0x5003,
RX_HOP_TABLE_ENTRY_2 = 0x5004,
RX_HOP_TABLE_ENTRY_3 = 0x5005,
RX_HOP_TABLE_ENTRY_4 = 0x5006,
RX_HOP_TABLE_ENTRY_5 = 0x5007,
RX_HOP_TABLE_ENTRY_6 = 0x5008,
RX_HOP_TABLE_ENTRY_7 = 0x5009,
RX_HOP_TABLE_ENTRY_8 = 0x500A,
RX_HOP_TABLE_ENTRY_9 = 0x500B,
RX_HOP_TABLE_ENTRY_10 = 0x500C,
RX_HOP_TABLE_ENTRY_11 = 0x500D,
RX_HOP_TABLE_ENTRY_12 = 0x500E,
RX_HOP_TABLE_ENTRY_13 = 0x500F,
RX_HOP_TABLE_ENTRY_14 = 0x5010,
RX_HOP_TABLE_ENTRY_15 = 0x5011,
RX_HOP_TABLE_ENTRY_16 = 0x5012,
RX_HOP_TABLE_ENTRY_17 = 0x5013,
RX_HOP_TABLE_ENTRY_18 = 0x5014,
RX_HOP_TABLE_ENTRY_19 = 0x5015,
RX_HOP_TABLE_ENTRY_20 = 0x5016,
RX_HOP_TABLE_ENTRY_21 = 0x5017,
RX_HOP_TABLE_ENTRY_22 = 0x5018,
RX_HOP_TABLE_ENTRY_23 = 0x5019,
RX_HOP_TABLE_ENTRY_24 = 0x501A,
RX_HOP_TABLE_ENTRY_25 = 0x501B,
RX_HOP_TABLE_ENTRY_26 = 0x501C,
RX_HOP_TABLE_ENTRY_27 = 0x501D,
RX_HOP_TABLE_ENTRY_28 = 0x501E,
RX_HOP_TABLE_ENTRY_29 = 0x501F,
RX_HOP_TABLE_ENTRY_30 = 0x5020,
RX_HOP_TABLE_ENTRY_31 = 0x5021,
RX_HOP_TABLE_ENTRY_32 = 0x5022,
RX_HOP_TABLE_ENTRY_33 = 0x5023,
RX_HOP_TABLE_ENTRY_34 = 0x5024,
RX_HOP_TABLE_ENTRY_35 = 0x5025,
RX_HOP_TABLE_ENTRY_36 = 0x5026,
RX_HOP_TABLE_ENTRY_37 = 0x5027,
RX_HOP_TABLE_ENTRY_38 = 0x5028,
RX_HOP_TABLE_ENTRY_39 = 0x5029,
RX_HOP_TABLE_ENTRY_40 = 0x502A,
RX_HOP_TABLE_ENTRY_41 = 0x502B,
RX_HOP_TABLE_ENTRY_42 = 0x502C,
RX_HOP_TABLE_ENTRY_43 = 0x502D,
RX_HOP_TABLE_ENTRY_44 = 0x502E,
RX_HOP_TABLE_ENTRY_45 = 0x502F,
RX_HOP_TABLE_ENTRY_46 = 0x5030,
RX_HOP_TABLE_ENTRY_47 = 0x5031,
RX_HOP_TABLE_ENTRY_48 = 0x5032,
RX_HOP_TABLE_ENTRY_49 = 0x5033,
RX_HOP_TABLE_ENTRY_50 = 0x5034,
RX_HOP_TABLE_ENTRY_51 = 0x5035,
RX_HOP_TABLE_ENTRY_52 = 0x5036,
RX_HOP_TABLE_ENTRY_53 = 0x5037,
RX_HOP_TABLE_ENTRY_54 = 0x5038,
RX_HOP_TABLE_ENTRY_55 = 0x5039,
RX_HOP_TABLE_ENTRY_56 = 0x503A,
RX_HOP_TABLE_ENTRY_57 = 0x503B,
RX_HOP_TABLE_ENTRY_58 = 0x503C,
RX_HOP_TABLE_ENTRY_59 = 0x503D,
RX_HOP_TABLE_ENTRY_60 = 0x503E,
RX_HOP_TABLE_ENTRY_61 = 0x503F,
RX_HOP_TABLE_ENTRY_62 = 0x5040,
RX_HOP_TABLE_ENTRY_63 = 0x5041
}SI446X_PROPERTY;
#endif //_SI446X_DEFS_H_
/*
=================================================================================
------------------------------------End of FILE----------------------------------
=================================================================================
*/
/****************************************************************************************************************************/
/*! @file radio_config.h
* @brief This file contains the automatically generated
* configurations.
*
* @n WDS GUI Version: 3.2.2.0
* @n Device: Si4463 Rev.: B1
*
* @b COPYRIGHT
* @n Silicon Laboratories Confidential
* @n Copyright 2013 Silicon Laboratories, Inc.
* @n http://www.silabs.com
*/
#ifndef RADIO_CONFIG_H_
#define RADIO_CONFIG_H_
// USER DEFINED PARAMETERS
// Define your own parameters here
// INPUT DATA
/*
//%% Crys_freq(Hz) Crys_tol(ppm) IF_mode High_perf_Ch_Fil OSRtune Ch_Fil_Bw_AFC ANT_DIV PM_pattern
// 30000000 10 2 1 0 1 0 0
//%% MOD_type Rsymb(sps) Fdev(Hz) RXBW(Hz) Mancheste AFC_en Rsymb_error Chip-Version
// 3 10000 20000 150000 0 1 0.0 2
//%% RF Freq.(MHz) API_TC fhst inputBW BERT RAW_dout D_source Hi_pfm_div
// 433 29 250000 0 0 0 0 1
//
// # WB filter 2 (BW = 68.71 kHz); NB-filter 4 (BW = 55.09 kHz)
//
// Modulation index: 4
*/
// CONFIGURATION PARAMETERS
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ {30000000L}
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER {0x00}
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH {0x07}
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP {0x03}
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET {0xF000}
#define RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD {0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5}
// CONFIGURATION COMMANDS
/*
// Command: RF_POWER_UP
// Description: Power-up the device with the specified function. Power-up is complete when the CTS bit is set. This command may take longer to set the CTS bit than other commands.
*/
#define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0xC9, 0xC3, 0x80
/*
// Command: RF_GPIO_PIN_CFG
// Description: Configures the gpio pins.
*/
#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x00, 0x20, 0x21, 0x00, 0x00
/*
// Set properties: RF_GLOBAL_XO_TUNE_1
// Number of properties: 1
// Group ID: 00
// Start ID: 00
// Default values: 0x40,
// Descriptions:
// GLOBAL_XO_TUNE - Crystal oscillator frequency tuning value. 0x00 is maximum frequency value and 0x7F is lowest frequency value. Each LSB code corresponds to a 70 fF capacitance change. The total adjustment range assuming a 30 MHz XTAL is +/-100 ppm.
*/
#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52
/*
// Set properties: RF_GLOBAL_CONFIG_1
// Number of properties: 1
// Group ID: 00
// Start ID: 03
// Default values: 0x20,
// Descriptions:
// GLOBAL_CONFIG - Various settings that affect entire chip. If PROTOCOL is specified, the chip is placed into protocol aware state.
*/
#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x40
/*
// Set properties: RF_INT_CTL_ENABLE_2
// Number of properties: 2
// Group ID: 01
// Start ID: 00
// Default values: 0x04, 0x00,
// Descriptions:
// INT_CTL_ENABLE - Enables top-level interrupt sources to generate HW interrupts at the NIRQ pin. The three interrupt groups are Chip, Modem and Packet Handler. Each of them contains multiple possible interrupt sources that must be individually enabled via the INT_CTL_PH_ENABLE, INT_CTL_MODEM_ENABLE, INT_CTL_CHIP_ENABLE properties. Note that this property only provides for global enabling/disabling of the HW interrupt indication on the NIRQ output pin. An internal interrupt event may still be generated even if the indication on the NIRQ output pin is disabled. The interrupt event may always be monitored by polling a GPIO pin, or via GET_INT_STATUS, GET_CHIP_STATUS, GET_PH_STATUS, or GET_MODEM_STATUS commands.
// INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group in order to generate a HW interrupt at the NIRQ output pin. In order to fully enable a HW interrupt, it is necessary to enable both the individual interrupt source (within this property) as well as the corresponding interrupt group (e.g., set INT_CTL_ENABLE:PH_INT_STATUS_EN). Note that even if an interrupt source is not enabled to generate a HW NIRQ interrupt, the given interrupt event still may occur inside the chip and may be monitored by polling a GPIO pin, or via the GET_INT_STATUS or GET_PH_STATUS commands.
*/
#define RF_INT_CTL_ENABLE_2 0x11, 0x01, 0x04, 0x00, 0x01, 0x38,0x00,0x00 //第一个字节代表属性配置入口，第2个字节代表组ID 0X0100就是1组，第3个字节代表要配置的寄存器个数
//第4个字节代表起始寄存器的地址，后面依次是要写入寄存器的值
/*
// Set properties: RF_FRR_CTL_A_MODE_4
// Number of properties: 4
// Group ID: 02
// Start ID: 00
// Default values: 0x01, 0x02, 0x09, 0x00,
// Descriptions:
// FRR_CTL_A_MODE - Set the data that is present in fast response register A.
// FRR_CTL_B_MODE - Set the data that is present in fast response register B.
// FRR_CTL_C_MODE - Set the data that is present in fast response register C.
// FRR_CTL_D_MODE - Set the data that is present in fast response register D.
*/
//#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00 //快速响应寄存器配置,4个都禁用
#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x04, 0x06, 0x0a, 0x00 //快速响应寄存器配置,A包处理程序中断挂起，MODEM 1T Pending，Latched RSSI
/*
// Set properties: RF_PREAMBLE_TX_LENGTH_9
// Number of properties: 9
// Group ID: 10
// Start ID: 00
// Default values: 0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00,
// Descriptions:
// PREAMBLE_TX_LENGTH - This property is used to configure the length of the Preamble field in TX mode for both Standard and Non-Standard Preambles. This property is not used by the chip in RX mode except when receiving a Non-Standard Preamble. In such a case, this property must be configured with the expected Preamble length (to provide an upper timeout limit on the Sync Word search algorithm). This property is only applicable in TX Packet Handler FIFO mode; if TX Direct Synchronous or TX Direct Asynchronous mode is selected (see MODEM_MOD_TYPE property), the entire transmission is obtained from a real-time TXDATA input stream on a GPIO pin and no automatic field construction is possible. The units of this property are in either nibbles or bytes, depending upon the value of PREAMBLE_CONFIG:LENGTH_CONFIG. Setting PREAMBLE_TX_LENGTH = 0x00 is a valid value, and will result in skipping transmission of the Preamble field; in such a case, the Sync Word will be the first transmitted field.
// PREAMBLE_CONFIG_STD_1 - The fields in this property are applicable only in RX mode, and apply primarily to reception of Standard Preamble patterns (e.g., 1010 or 0101 patterns). However, see note on required configuration of RX_THRESH during reception of Non-Standard Preamble patterns.
// PREAMBLE_CONFIG_NSTD - The fields in this property apply only to transmission and reception of packets with Non-Standard Preamble patterns (e.g., other than 1010 or 0101 patterns).
// PREAMBLE_CONFIG_STD_2 - During initial reception and acquisition of a packet, it is often useful to define a timeout period to limit the amount of time the chip remains on-channel awaiting the incoming packet. This property allows configuration of this preamble search timeout period. If a valid preamble is not found within the specified timeout period, an INVALID_PREAMBLE event is generated and may be used to generate an interrupt and/or exit automatically from RX mode. The fields in this property are applicable only in RX mode, and only apply to reception of Standard Preamble patterns (e.g., 1010 or 0101 patterns). Detection of INVALID_PREAMBLE is not possible when configured to receive a Non-Standard Preamble pattern. Two different timeout configuration fields are provided to allow definition of timeout periods with significantly different lengths and bit resolution.
// PREAMBLE_CONFIG - Miscellaneous preamble configuration bits.
// PREAMBLE_PATTERN_31_24 - The PREAMBLE_PATTERN_XX properties define the pattern to be transmitted in TX mode and the pattern expected to be received in RX mode, but only when PREAMBLE_CONFIG:STANDARD_PREAM has been set to 0x0 (i.e., use Non-Standard Preamble). The PREAMBLE_PATTERN_XX properties are used to define the actual bit values describing the Non-Standard Preamble pattern; PREAMBLE_CONFIG_NSTD:PATTERN_LENGTH is used to define how many bits of the PREAMBLE_PATTERN_XX values are used. In TX mode, if the value of PREAMBLE_TX_LENGTH is larger than PREAMBLE_CONFIG_NSTD:PATTERN_LENGTH, the PREAMBLE_PATTERN will be transmitted repeatedly until the full number of bits has been sent. In RX mode, the full number of bits defined by PREAMBLE_CONFIG_NSTD:PATTERN_LENGTH must be received once before the PREAMBLE_VALID signal/interrupt is generated. If Manchester encoding/decoding is enabled, the values of the PREAMBLE_PATTERN_XX properties are expressed in chips (i.e., after Manchester encoding in TX mode, or before Manchester decoding in RX mode). The bits of the PREAMBLE_PATTERN_XX are always sent bits 0-31 time-wise (e.g., PREAMBLE_PATTERN_7_0 bit 0 is sent first).
// PREAMBLE_PATTERN_23_16 - Bits 23-16 of the Non-Standard Preamble pattern to be transmitted or expected to be received. Please refer to the text description for PREAMBLE_PATTERN_31_24 for more details regarding the Non-Standard Preamble functionality.
// PREAMBLE_PATTERN_15_8 - Bits 15-8 of the Non-Standard Preamble pattern to be transmitted or expected to be received. Please refer to the text description for PREAMBLE_PATTERN_31_24 for more details regarding the Non-Standard Preamble functionality.
// PREAMBLE_PATTERN_7_0 - Bits 7-0 of the Non-Standard Preamble pattern to be transmitted or expected to be received. Please refer to the text description for PREAMBLE_PATTERN_31_24 for more details regarding the Non-Standard Preamble functionality.
*/
#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x0A, 0x14, 0x00, 0x10, 0x31, 0x00, 0x00, 0x00, 0x00 //前同步码配置
/*
// Set properties: RF_SYNC_CONFIG_5
// Number of properties: 5
// Group ID: 11
// Start ID: 00
// Default values: 0x01, 0x2D, 0xD4, 0x2D, 0xD4,
// Descriptions:
// SYNC_CONFIG - Configuration of miscellaneous Sync Word bits. NOTE: each byte of the Sync Word is transmitted/received in little-endian fashion (i.e., least significant bit first). Byte(s) of the Sync Word are transmitted/received in descending order (i.e., Byte 3 first, followed by Byte 2, etc.)
// SYNC_BITS_31_24 - Define the value of Byte 3 of the Sync Word for both TX and RX operation. NOTE: Although the Sync Word byte(s) are transmitted/received in descending order (i.e., Byte 3 first, followed by Byte 2, etc.), each byte is transmitted/received in little-endian fashion (i.e., least significant bit first).
// SYNC_BITS_23_16 - Sync bytes are always sent bit 0 first.
// SYNC_BITS_15_8 - Sync bytes are always sent bit 0 first.
// SYNC_BITS_7_0 - Sync bytes are always sent bit 0 first.
*/
//同步字配置，0x1100,0x1101,0x1102,0x1103,0x1104 5个寄存器 同步字使用2和3，共2个字节，同步字3为0XB4,同步字2为0X2B,同步字1为0x00，同步字0为0X00
#define RF_SYNC_CONFIG_5 0x11, 0x11, 0x05, 0x00, 0x01, 0xB4, 0x2B, 0x00, 0x00 //第一个字节代表属性配置入口，第2个字节代表组ID 0X0100就是1组，第3个字节代表要配置的寄存器个数
//第4个字节代表起始寄存器的地址，后面依次是要写入寄存器的值
/*
// Set properties: RF_PKT_CRC_CONFIG_1
// Number of properties: 1
// Group ID: 12
// Start ID: 00
// Default values: 0x00,
// Descriptions:
// PKT_CRC_CONFIG - The chip contains a 32-bit CRC engine for the purpose of generating and comparing a checksum across selected data fields. This property is used to select the desired CRC polynomial and CRC seed value. If a 8-bit CRC polynomial is selected, the length of the resulting checksum is 1-bytes. If a 16-bit CRC polynomial is selected, the length of the resulting checksum is 2-bytes. If a 32-bit CRC polynomial is selected, the length of the resulting checksum is 4-bytes. The configuration bits in this property are common to both TX and RX modes; however, this property is only applicable when automatic Packet Handling is enabled (e.g., when using the TX FIFO as the modulation source in TX mode, or when PKT_CONFIG1:PH_RX_DISABLE is cleared in RX mode).
*/
#define RF_PKT_CRC_CONFIG_1 0x11, 0x12, 0x01, 0x00, 0x84 //CRC校验设置，使用1s作为CRC种子，CRC16(IBM)校验方式
/*
// Set properties: RF_PKT_CONFIG1_1
// Number of properties: 1
// Group ID: 12
// Start ID: 06
// Default values: 0x00,
// Descriptions:
// PKT_CONFIG1 - General packet configuration bits.
*/
#define RF_PKT_CONFIG1_1 0x11, 0x12, 0x01, 0x06, 0x12 //通 用包配置 ，数据包接收完后离开接收通道，CRC高字节先传送 0X1206寄存器
/*
// Set properties: RF_PKT_LEN_3
// Number of properties: 3
// Group ID: 12
// Start ID: 08
// Default values: 0x00, 0x00, 0x00,
// Descriptions:
// PKT_LEN - This property configures the chip for reception of a variable length packet. This property is applicable only in RX mode, and only when the automatic Packet Handler is enabled (i.e., PKT_CONFIG1:PH_RX_DISABLE is cleared). If enabled, the extracted length can be retrieved using the PACKET_INFO command.
// PKT_LEN_FIELD_SOURCE - This property configures the chip for reception of a variable length packet, and defines where the length field is in the packet. The packet length byte(s) must be the last byte(s) in a fixed length field and must precede the variable length field. This property is applicable only in RX mode, and only when the automatic Packet Handler is enabled (i.e., the PH_RX_DISABLE bit in the PKT_CONFIG1 property is cleared).
// PKT_LEN_ADJUST - It is possible to define the total length of a packet in a variety of ways (e.g., including/excluding the packet length bytes, including/excluding the CRC bytes, etc.) This property provides a means of adjusting/offsetting the received packet length value in order to comply with a wide range of packet length implementations. This property is applicable only in RX mode, and only when the automatic Packet Handler is enabled (i.e., the PH_RX_DISABLE bit in the PKT_CONFIG1 property is cleared). The value of the LEN_ADJUST field is added to the received value of the packet length byte(s), extracted from the field specified by the SRC_FIELD value in the PKT_LEN_FIELD_SOURCE property. The resulting value is then used to configure the length of the variable length field specified by PKT_LEN:DST_FIELD. The required constant value of the LEN_ADJUST field is typically defined in a protocol specification or regulatory standard, or can be derived from the specification. The default processing mode of the chip is that the received packet length value does NOT include the packet length bytes, and does NOT include CRC bytes. In such a case, the LEN_ADJUST field should be set to 0x00. If the received packet length value includes the packet length bytes and/or the CRC bytes, its effective value must be reduced by adding a negative offset. In such a case, the LEN_ADJUST field should be set to the negative value of the extra byte count (in 2's complement format). Example: the transmitted packet has a 2-byte packet length field followed by a 10-byte Payload field, and the value contained in the packet length bytes = 0x000C = 12 bytes. The value of LEN_ADJUST should be set = 0xFE = -2. The LEN_ADJUST field is a signed value.
*/
#define RF_PKT_LEN_3 0x11, 0x12, 0x03, 0x08, 0x00, 0x00, 0x00 //包长度设置，长度字段至少一个字节，设置为1个有效字节，
/*
// Set properties: RF_PKT_FIELD_1_LENGTH_12_8_12
// Number of properties: 12
// Group ID: 12
// Start ID: 0D
// Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
// Descriptions:
// PKT_FIELD_1_LENGTH_12_8 - The PKT_FIELD_1_LENGTH_XX properties specify the length of Field 1 in bytes. The field length is an unsigned 13-bit value; this property is Byte 1 of the length value, and is used along with the PKT_FIELD_1_LENGTH_7_0 property. Partitioning of the Payload into separate fields is provided to support variable length packets, and to allow different forms of data processing (e.g., Manchester encoding, data whitening, etc) across different fields. These properties are applicable in TX mode only if the START_TX command is sent with the parameter TX_LEN=0. These properties are applicable in RX mode only under the following conditions: RX Packet Handling is enabled by clearing PKT_CONFIG1:PH_RX_DISABLE, and The START_RX command is sent with the parameter RX_LEN=0, and PKT_CONFIG1:PH_FIELD_SPLIT is cleared. If the PH_FIELD_SPLIT bit is set, the lengths of the various fields in RX mode are determined by the PKT_RX_FIELD_LENGTH_XX properties. A value of zero in this property means that the field is not used. During TX mode, data will be retrieved from the TX FIFO until encountering the first field whose length has been set to zero. During RX mode, data will be stored in the RX FIFO until again encountering the first field whose length has been set to zero. It is possible (although not common) to set the length of Field 1 = 0 bytes, as this would indicate transmission/reception of a packet with no Payload data at all. Field 1 cannot be configured as a variable length field, as there is no preceding field that may contain the variable length byte(s).
// PKT_FIELD_1_LENGTH_7_0 - Byte 0 of the unsigned 13-bit Field 1 length value. Please refer to the text description for PKT_FIELD_1_LENGTH_12_8 for more details regarding Field 1 length configuration.
// PKT_FIELD_1_CONFIG - Partitioning of the Payload into separate fields is provided to support features such as variable length packets and field-specific data processing (e.g., Manchester encoding, data whitening, etc). This property provides configuration bits for field-specific processing on Field 1. The configuration bits in this property are common to both TX and RX modes dependent on PKT_CONFIG1:PH_FIELD_SPLIT; however, this property is only applicable when automatic Packet Handling is enabled (e.g., when using the TX FIFO as the modulation source in TX mode, or when PKT_CONFIG1:PH_RX_DISABLE is cleared in RX mode).
// PKT_FIELD_1_CRC_CONFIG - This property is use to control the calculation, transmission, and checking of CRC across Field 1.
// PKT_FIELD_2_LENGTH_12_8 - The PKT_FIELD_2_LENGTH_XX properties specify the length of Field 2 in bytes. The field length is an unsigned 13-bit value; this property is Byte 1 of the length value, and is used along with the PKT_FIELD_2_LENGTH_7_0 property. Field 2 may be configured as a variable length field by setting the appropriate value of DST_FIELD (in the PKT_LEN property); however, it is also necessary that a previous field contain the variable length byte(s). If configured as a variable length field, this property must be set with a value that represents the maximum expected length of the field. Please refer to the text description for PKT_FIELD_1_LENGTH_12_8 for more details regarding field length configuration.
// PKT_FIELD_2_LENGTH_7_0 - Byte 0 of the unsigned 13-bit Field 2 length value. Please refer to the text description for PKT_FIELD_2_LENGTH_12_8 for more details regarding Field 2 length configuration.
// PKT_FIELD_2_CONFIG - This property provides configuration bits for field-specific processing on Field 2. Please refer to the text description for PKT_FIELD_1_CONFIG for more details regarding enabling/disabling of field-specific processing.
// PKT_FIELD_2_CRC_CONFIG - This property is use to control the calculation, transmission, and checking of CRC across Field 2. Please refer to the text description for PKT_FIELD_1_CRC_CONFIG for more details regarding configuration of field-specific CRC calculation.
// PKT_FIELD_3_LENGTH_12_8 - The PKT_FIELD_3_LENGTH_XX properties specify the length of Field 3 in bytes. The field length is an unsigned 13-bit value; this property is Byte 1 of the length value, and is used along with the PKT_FIELD_3_LENGTH_7_0 property. Field 3 may be configured as a variable length field by setting the appropriate value of DST_FIELD (in the PKT_LEN property); however, it is also necessary that a previous field contain the variable length byte(s). If configured as a variable length field, this property must be set with a value that represents the maximum expected length of the field. Please refer to the text description for PKT_FIELD_1_LENGTH_12_8 for more details regarding field length configuration.
// PKT_FIELD_3_LENGTH_7_0 - Byte 0 of the unsigned 13-bit Field 3 length value. Please refer to the text description for PKT_FIELD_3_LENGTH_12_8 for more details regarding Field 3 length configuration.
// PKT_FIELD_3_CONFIG - This property provides configuration bits for field-specific processing on Field 3. Please refer to the text description for PKT_FIELD_1_CONFIG for more details regarding enabling/disabling of field-specific processing.
// PKT_FIELD_3_CRC_CONFIG - This property is use to control the calculation, transmission, and checking of CRC across Field 3. Please refer to the text description for PKT_FIELD_1_CRC_CONFIG for more details regarding configuration of field-specific CRC calculation.
*/
#define RF_PKT_FIELD_1_LENGTH_12_8_12 0x11, 0x12, 0x0C, 0x0D, 0x00, 0x07, 0x04, 0x8A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 //字段长度设置
/*
// Set properties: RF_PKT_FIELD_4_LENGTH_12_8_8
// Number of properties: 8
// Group ID: 12
// Start ID: 19
// Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
// Descriptions:
// PKT_FIELD_4_LENGTH_12_8 - The PKT_FIELD_4_LENGTH_XX properties specify the length of Field 4 in bytes. The field length is an unsigned 13-bit value; this property is Byte 1 of the length value, and is used along with the PKT_FIELD_4_LENGTH_7_0 property. Field 4 may be configured as a variable length field by setting the appropriate value of DST_FIELD (in the PKT_LEN property); however, it is also necessary that a previous field contain the variable length byte(s). If configured as a variable length field, this property must be set with a value that represents the maximum expected length of the field. Please refer to the text description for PKT_FIELD_1_LENGTH_12_8 for more details regarding field length configuration.
// PKT_FIELD_4_LENGTH_7_0 - Byte 0 of the unsigned 13-bit Field 4 length value. Please refer to the text description for PKT_FIELD_4_LENGTH_12_8 for more details regarding Field 4 length configuration.
// PKT_FIELD_4_CONFIG - This property provides configuration bits for field-specific processing on Field 4. Please refer to the text description for PKT_FIELD_1_CONFIG for more details regarding enabling/disabling of field-specific processing.
// PKT_FIELD_4_CRC_CONFIG - This property is use to control the calculation, transmission, and checking of CRC across Field 4. Please refer to the text description for PKT_FIELD_1_CRC_CONFIG for more details regarding configuration of field-specific CRC calculation.
// PKT_FIELD_5_LENGTH_12_8 - The PKT_FIELD_5_LENGTH_XX properties specify the length of Field 5 in bytes. The field length is an unsigned 13-bit value; this property is Byte 1 of the length value, and is used along with the PKT_FIELD_5_LENGTH_7_0 property. Field 5 may be configured as a variable length field by setting the appropriate value of DST_FIELD (in the PKT_LEN property); however, it is also necessary that a previous field contain the variable length byte(s). If configured as a variable length field, this property must be set with a value that represents the maximum expected length of the field. Please refer to the text description for PKT_FIELD_1_LENGTH_12_8 for more details regarding field length configuration.
// PKT_FIELD_5_LENGTH_7_0 - Byte 0 of the unsigned 13-bit Field 5 length value. Please refer to the text description for PKT_FIELD_5_LENGTH_12_8 for more details regarding Field 5 length configuration.
// PKT_FIELD_5_CONFIG - This property provides configuration bits for field-specific processing on Field 5. Please refer to the text description for PKT_FIELD_1_CONFIG for more details regarding enabling/disabling of field-specific processing.
// PKT_FIELD_5_CRC_CONFIG - This property is use to control the calculation, transmission, and checking of CRC across Field 5. Please refer to the text description for PKT_FIELD_1_CRC_CONFIG for more details regarding configuration of field-specific CRC calculation.
*/
#define RF_PKT_FIELD_4_LENGTH_12_8_8 0x11, 0x12, 0x08, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
/*
// Set properties: RF_MODEM_MOD_TYPE_12
// Number of properties: 12
// Group ID: 20
// Start ID: 00
// Default values: 0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06,
// Descriptions:
// MODEM_MOD_TYPE - This property configures the Modem in the chip for transmission/reception of the following modulation types: OOK, 2(G)FSK, and 4(G)FSK (if supported) modulation. In TX mode, this property is additionally used to select the source of the TX data stream, and whether that TX data stream is from a synchronous or asynchronous source (in Direct mode only). The Modem must be configured for transmission/reception of only one type of modulation throughout the entire packet; it is not possible (for example) to use OOK modulation over certain fields and (G)FSK modulation over other fields. If 4(G)FSK is supported, it is possible to switch between 2(G)FSK and 4(G)FSK on a field-specific basis; however, this is accomplished by configuring the Modem to 4(G)FSK mode for the entire packet and then performing special data processing in the Packet Handler.
// MODEM_MAP_CONTROL - Modem Mapping Control.
// MODEM_DSM_CTRL - Delta Sigma Modulator control.
// MODEM_DATA_RATE_2 - Data rate, unsigned 24-bit, 100 kbps by default.
// MODEM_DATA_RATE_1 - Data rate, unsigned 24-bit, 100 kbps by default.
// MODEM_DATA_RATE_0 - Data rate, unsigned 24-bit, 100 kbps by default.
// MODEM_TX_NCO_MODE_3 - TX NCOs modulo, unsigned 26-bit, default value is 0x1C9C380. Together with the crystal frequency and data rate, this number will set the symbol rate. If data rate is greater than 50 kbps, it should be set to 0x1C9C380. Otherwise it will be 0x2DC6C0.
// MODEM_TX_NCO_MODE_2 - TX NCOs modulo, unsigned 26-bit, default value is 0x1C9C380. Together with the crystal frequency and data rate, this number will set the symbol rate. If data rate is greater than 50 kbps, it should be set to 0x1C9C380. Otherwise it will be 0x2DC6C0.
// MODEM_TX_NCO_MODE_1 - TX NCOs modulo, unsigned 26-bit, default value is 0x1C9C380. Together with the crystal frequency and data rate, this number will set the symbol rate. If data rate is greater than 50 kbps, it should be set to 0x1C9C380. Otherwise it will be 0x2DC6C0.
// MODEM_TX_NCO_MODE_0 - TX NCOs modulo, unsigned 26-bit, default value is 0x1C9C380. Together with the crystal frequency and data rate, this number will set the symbol rate. If data rate is greater than 50 kbps, it should be set to 0x1C9C380. Otherwise it will be 0x2DC6C0.
// MODEM_FREQ_DEV_2 - The TX frequency deviation is specified by an unsigned 17-bit value. This property defines Byte 2 of the frequency deviation value. The units of the MODEM_FREQ_DEV_X property are in increments of the LSB tuning resolution of the PLL Synthesizer, and are therefore a function of the crystal frequency and output frequency band. The formula for calculating the value of the MODEM_FREQ_DEV property is given by the following equation: For 2(G)FSK mode, the specified value is the peak deviation. For 4(G)FSK mode (if supported), the specified value is the inner deviation (i.e., between channel center frequency and the nearest symbol deviation level). The MODEM_FREQ_DEV_X properties are only used in TX mode.
// MODEM_FREQ_DEV_1 - The TX frequency deviation is specified by an unsigned 17-bit value. This property defines Byte 1 of the frequency deviation value. Please refer to the text description for MODEM_FREQ_DEV_2 for more details regarding TX frequency deviation.
*/
#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x00, 0x9C, 0x40, 0x04, 0x2D, 0xC6, 0xC0, 0x00, 0x05 //调制类型设置2GFSK 0x03，禁用曼彻斯特编码
//波特率设置 40KHZ 0x009c40 ,3M时钟速率0x002DC6C0
//波特率设置：0x009C40 10KHZ,频偏高8位设置0X05***********/
/***********
#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x06, 0x1A, 0x80, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x05调制类型设置2GFSK 0x03，禁用曼彻斯特编码
//波特率设置 40KHZ 0x009c40 30M时钟速率 0x01C9C38
//波特率设置： 0x06, 0x1A, 0x80 10KHZ,频偏高8位设置0X05
***********************/
/*
// Set properties: RF_MODEM_FREQ_DEV_0_1
// Number of properties: 1
// Group ID: 20
// Start ID: 0C
// Default values: 0xD3,
// Descriptions:
// MODEM_FREQ_DEV_0 - The TX frequency deviation is specified by an unsigned 17-bit value. This property defines Byte 0 of the frequency deviation value. Please refer to the text description for MODEM_FREQ_DEV_2 for more details regarding TX frequency deviation.
*/
#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x76 //频偏字节0设置 0X000576 频偏20kHZ
/*
// Set properties: RF_MODEM_TX_RAMP_DELAY_8
// Number of properties: 8
// Group ID: 20
// Start ID: 18
// Default values: 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20,
// Descriptions:
// MODEM_TX_RAMP_DELAY - Unit in TX bit cycle, it is calculated according to modulation type.
// MODEM_MDM_CTRL - Detector selection and PM pattern configuration.
// MODEM_IF_CONTROL - Specifies fixed-IF(468.75 kHz), zero-IF, or scalable IF.
// MODEM_IF_FREQ_2 - Bits 16 an 17 of the 18-bit IF frequency. Specify fixed-IF(468.75kHz), zero-IF, or scalable IF.
// MODEM_IF_FREQ_1 - IF frequency is 18-bit.
// MODEM_IF_FREQ_0 - IF frequency is 18-bit.
// MODEM_DECIMATION_CFG1 - Specifies the exponent of decimation ratios of the three CIC decimators in RX filter chain.
// MODEM_DECIMATION_CFG0 - This property specifies the selection of the two polyphase filters preceding CIC filters, the droop compensation filter, the RX decimate by 8 2x filter and the channel filter power mode.
*/
#define RF_MODEM_TX_RAMP_DELAY_8 0x11, 0x20, 0x08, 0x18, 0x01, 0x80, 0x08, 0x03, 0x80, 0x00, 0x20, 0x10
/*
// Set properties: RF_MODEM_BCR_OSR_1_9
// Number of properties: 9
// Group ID: 20
// Start ID: 22
// Default values: 0x00, 0x4B, 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0,
// Descriptions:
// MODEM_BCR_OSR_1 - High byte of RX symbol oversampling rate at BCR/Slicer (12-bit unsigned number).
// MODEM_BCR_OSR_0 - Low byte of RX symbol oversampling rate at BCR/Slicer, total 12 bits.
// MODEM_BCR_NCO_OFFSET_2 - Specifies the 6 MSBs of the BCR NCO offset.
// MODEM_BCR_NCO_OFFSET_1 - Byte 1 of RX BCR NCO offset (an unsigned 22-bit number).
// MODEM_BCR_NCO_OFFSET_0 - Low byte of RX NCO offset.
// MODEM_BCR_GAIN_1 - High byte of clock recovery timing loop gain value.
// MODEM_BCR_GAIN_0 - Low byte of clock recovery timing loop gain value.
// MODEM_BCR_GEAR - RX BCR loop gear control. A reduced value of bit clock recovery gain is often desired after gear shifting (to reduce clock jitter). The BCR loop gain in both gear modes is obtained from a baseline clock recovery gain value (crgain in the MODEM_BCR_GAIN_x properties), scaled by the crfast and crslow values specified in this property. NOTE: larger values of crfast or crslow result in lower values of bit clock recovery gain.
// MODEM_BCR_MISC1 - This property configures miscellaneous options within the RX BCR loop.
*/
#define RF_MODEM_BCR_OSR_1_9 0x11, 0x20, 0x09, 0x22, 0x00, 0xFA, 0x02, 0x0C, 0x4A, 0x01, 0x06, 0x02, 0xC2
/*
// Set properties: RF_MODEM_AFC_GEAR_7
// Number of properties: 7
// Group ID: 20
// Start ID: 2C
// Default values: 0x00, 0x23, 0x83, 0x69, 0x00, 0x40, 0xA0,
// Descriptions:
// MODEM_AFC_GEAR - Selection of gear switching source for both RX AFC and BCR. Control of gain for RX AFC in both FAST and SLOW modes (i.e., before and after gear switching)
// MODEM_AFC_WAIT - Short and long wait periods after AFC correction.
// MODEM_AFC_GAIN_1 - High byte of 13-bit AFC loop gain value. Enabling of AFC frequency error estimation. Enabling of dynamic IF bandwidth switching during the packet.
// MODEM_AFC_GAIN_0 - Low byte of 13-bit AFC loop gain value
// MODEM_AFC_LIMITER_1 - High byte of 15-bit AFC limiter value.
// MODEM_AFC_LIMITER_0 - Low byte of 15-bit AFC limiter value.
// MODEM_AFC_MISC - Specifies misc AFC control bits.
*/
#define RF_MODEM_AFC_GEAR_7 0x11, 0x20, 0x07, 0x2C, 0x04, 0x36, 0xC0, 0x1D, 0x0D, 0x58, 0xC0
/*
// Set properties: RF_MODEM_AGC_CONTROL_1
// Number of properties: 1
// Group ID: 20
// Start ID: 35
// Default values: 0xE0,
// Descriptions:
// MODEM_AGC_CONTROL - AGC control.
*/
#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE2 //AGC增益控制
/*
// Set properties: RF_MODEM_AGC_WINDOW_SIZE_9
// Number of properties: 9
// Group ID: 20
// Start ID: 38
// Default values: 0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B,
// Descriptions:
// MODEM_AGC_WINDOW_SIZE - Sets PGA and LNA settling time window and measurement time window.
// MODEM_AGC_RFPD_DECAY - Sets RF detector decay time.
// MODEM_AGC_IFPD_DECAY - Sets IF detector decay time.
// MODEM_FSK4_GAIN1 - Controls 4(G)FSK suppression gain.
// MODEM_FSK4_GAIN0 - Controls 4(G)FSK suppression gain.
// MODEM_FSK4_TH1 - High byte of 4(G)FSK slicer threshold.
// MODEM_FSK4_TH0 - Low byte of 4(G)FSK slicer threshold.
// MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
// MODEM_OOK_PDTC - OOK peak detector decay and attack time.
*/
#define RF_MODEM_AGC_WINDOW_SIZE_9 0x11, 0x20, 0x09, 0x38, 0x11, 0x37, 0x37, 0x00, 0x1A, 0x10, 0x00, 0x00, 0x29
/*
// Set properties: RF_MODEM_OOK_CNT1_11
// Number of properties: 11
// Group ID: 20
// Start ID: 42
// Default values: 0xA4, 0x03, 0x56, 0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01,
// Descriptions:
// MODEM_OOK_CNT1 - OOK control.
// MODEM_OOK_MISC - Control OOK Peak Detector.
// MODEM_RAW_SEARCH - Searching period for high and low gear.
// MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
// MODEM_RAW_EYE_1 - Eye-open detector threshold.
// MODEM_RAW_EYE_0 - Eye-open detector threshold. The reset of bits are set by property RAW_EYE_1.
// MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
// MODEM_ANT_DIV_CONTROL - Specifies pm detection threshold and GPIO configuration in antenna diversity mode.
// MODEM_RSSI_THRESH - Selects the threshold for Clear Channel Assessment (CCA) and generation of the RSSI interrupt. If the Current RSSI value is above this threshold, a GPIO pin configured to output the CCA signal will be high. If the Current RSSI value crosses above this threshold, the RSSI interrupt will be generated. NOTE: the Latched RSSI value exceeding this threshold will not generate an RSSI interrupt. If enabled in the MODEM_RSSI_CONTROL property, the Latched RSSI value may also be compared against this threshold. The purpose of the comparison is to determine if the Latched RSSI value is below (not above) the threshold; if so, the chip proceeds to the specified START_RX:RXTIMEOUT_STATE and generates a PREAMBLE_INVALID interrupt.
// MODEM_RSSI_JUMP_THRESH - RSSI jumping detection threshold, step in 1 dB.
// MODEM_RSSI_CONTROL - Selects if the RSSI value is latched, and at what point in the packet it is latched. The Latched RSSI value may be read by a Fast Response Register, or returned by the GET_MODEM_STATUS command. Selects whether the RSSI value is updated every 1*Tb bit period, or whether the RSSI value is averaged over the previous 4*Tb bit periods. Selects if the Latched RSSI value is compared against the MODEM_RSSI_THRESH value, for the purpose of exiting to the RXTIMEOUT_STATE if below threshold.
*/
#define RF_MODEM_OOK_CNT1_11 0x11, 0x20, 0x0B, 0x42, 0xA4, 0x02, 0xD6, 0x83, 0x01, 0xFF, 0x01, 0x80, 0xFF, 0x0C, 0x12 //RSSI average over 4 bits, latches at sync word detect
/*
// Set properties: RF_MODEM_RSSI_COMP_1
// Number of properties: 1
// Group ID: 20
// Start ID: 4E
// Default values: 0x32,
// Descriptions:
// MODEM_RSSI_COMP - Offsets RSSI curve in 1 dB steps. 32 is no offset, lower will adjust RSSI down, and higher will adjust RSSI up.
*/
#define RF_MODEM_RSSI_COMP_1 0x11, 0x20, 0x01, 0x4E, 0x40 //RSSI 补偿
/*
// Set properties: RF_MODEM_CLKGEN_BAND_1
// Number of properties: 1
// Group ID: 20
// Start ID: 51
// Default values: 0x08,
// Descriptions:
// MODEM_CLKGEN_BAND - Selects the divide ratio of the configurable divider at the output of the PLL Synthesizer as a function of the desired operating frequency band. Configures the PLL Synthesizer for High Performance or Low Power operating mode, allowing a tradeoff between tuning resolution and current consumption.
*/
#define RF_MODEM_CLKGEN_BAND_1 0x11, 0x20, 0x01, 0x51, 0x0A
/*
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
// Number of properties: 12
// Group ID: 21
// Start ID: 00
// Default values: 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01,
// Descriptions:
// MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - The chip implements the RX channel selection bandpass filtering in the digital domain as an FIR filter. The MODEM_CHFLT_RX_CHFLT_COEXX properties define the values for the filter tap coefficients. The chip provides for two different sets of RX filter coefficients (MODEM_CHFLT_RX1 and MODEM_CHFLT_RX2). These properties define the values for the first set of filter coefficients; see also the text description for the MODEM_CHFLT_RX2_CHFLT_COEXX properties for a discussion of the second set of filter coefficients and use of adaptive RX filter bandwidth across the packet. By default, the digital filter is 27 taps in length. However, it is possible to configure the RX Modem for a channel selection filter with only 15 taps; the advantage of the 15-tap filter is a reduction in filter processing delay at the expense of reduced filtering performance (e.g., adjacent channel selectivity). Please contact Silicon Labs for assistance with configuring the reduced performance filter. The values of the tap coefficients are symmetrical; that is, the value of COEFF26=COEFF0, COEFF25=COEFF1, and so on. Thus it is only necessary to store 14 filter coefficients; the internal circuitry obtains the remaining coefficients through symmetry. Each filter tap coefficient is a 10-bit signed value. The lower 8-bits of each coefficient are held in the MODEM_CHFLT_RX1_CHFLT_COEXX properties; the top two bits are packed into the MODEM_CHFLT_RX1_CHFLT_COEMXX properties. Silicon Labs has pre-calculated 15 different sets of filter tap coefficients. The WDS Calculator will recommend one of these filter sets, based upon the RX filter bandwidth required to receive the desired signal. The filter bandwidth is a function of both the selected filter set, as well as the filter clock decimation ratio (see the MODEM_DECIMATION_CFG1/0 properties). This property sets the lower 8-bits of the 13th filter coefficient for the first set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX1_CHFLT_COEM0 property.
// MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - This property sets the lower 8-bits of the 12th filter coefficient for the first set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX1_CHFLT_COEM0 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - This property sets the lower 8-bits of the 11th filter coefficient for the first set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX1_CHFLT_COEM0 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - This property sets the lower 8-bits of the 10th filter coefficient for the first set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX1_CHFLT_COEM0 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - This property sets the lower 8-bits of the 9th filter coefficient for the first set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX1_CHFLT_COEM1 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - This property sets the lower 8-bits of the 8th filter coefficient for the first set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX1_CHFLT_COEM1 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - This property sets the lower 8-bits of the 7th filter coefficient for the first set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX1_CHFLT_COEM1 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - This property sets the lower 8-bits of the 6th filter coefficient for the first set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX1_CHFLT_COEM1 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - This property sets the lower 8-bits of the 5th filter coefficient for the first set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX1_CHFLT_COEM2 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - This property sets the lower 8-bits of the 4th filter coefficient for the first set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX1_CHFLT_COEM2 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - This property sets the lower 8-bits of the 3rd filter coefficient for the first set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX1_CHFLT_COEM2 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - This property sets the lower 8-bits of the 2nd filter coefficient for the first set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX1_CHFLT_COEM2 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
*/
#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C
/*
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
// Number of properties: 12
// Group ID: 21
// Start ID: 0C
// Default values: 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5,
// Descriptions:
// MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - This property sets the lower 8-bits of the 1st filter coefficient for the first set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX1_CHFLT_COEM3 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - This property sets the lower 8-bits of the 0th filter coefficient for the first set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX1_CHFLT_COEM3 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX1_CHFLT_COEM0 - There are 14 filter tap coefficient values; each value is a signed 10-bit value. The lower 8-bits of each coefficient are set in the MODEM_CHFLT_RX_CHFLT_COEXX properties, while the top two bits are packed into the MODEM_CHFLT_RX_CHFLT_COEMXX properties. This property contains the top two bits of the 13th through 10th filter coefficients for the first set of filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COEM1 - There are 14 filter tap coefficient values; each value is a signed 10-bit value. The lower 8-bits of each coefficient are set in the MODEM_CHFLT_RX_CHFLT_COEXX properties, while the top two bits are packed into the MODEM_CHFLT_RX_CHFLT_COEMXX properties. This property contains the top two bits of the 9th through 6th filter coefficients for the first set of filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COEM2 - There are 14 filter tap coefficient values; each value is a signed 10-bit value. The lower 8-bits of each coefficient are set in the MODEM_CHFLT_RX_CHFLT_COEXX properties, while the top two bits are packed into the MODEM_CHFLT_RX_CHFLT_COEMXX properties. This property contains the top two bits of the 5th through 2nd filter coefficients for the first set of filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COEM3 - There are 14 filter tap coefficient values; each value is a signed 10-bit value. The lower 8-bits of each coefficient are set in the MODEM_CHFLT_RX_CHFLT_COEXX properties, while the top two bits are packed into the MODEM_CHFLT_RX_CHFLT_COEMXX properties. This property contains the top two bits of the 1st through 0th filter coefficients for the first set of filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - The chip provides for two different sets of RX filter coefficients (MODEM_CHFLT_RX1 and MODEM_CHFLT_RX2). These properties define the values for the second set of filter coefficients; see also the text description for the MODEM_CHFLT_RX1_CHFLT_COEXX properties for a general discussion of the configuration of filter tap coefficients. Two different sets of filter tap coefficients (i.e., filter bandwidths) are provided to allow narrowing the RX bandwidth after the PLL-based AFC algorithm has acquired the signal and centered it in the filter passband. With no residual frequency error, the filter bandwidth may be reduced to pass only the modulation bandwidth of the signal, thus improving sensitivity over the remainder of the packet. This adaptive RX bandwidth feature is only applicable when PLL AFC is enabled (by setting MODEM_AFC_MISC:ENFBPLL), and the adaptive RX bandwidth function is enabled (by setting MODEM_AFC_GAIN_1:AFCBD). When the adaptive RX bandwidth feature is enabled, the first set of filter coefficients (defined in the MODEM_CHFLT_RX1 properties) is effective prior to gear-switching (e.g., detection of PREAMBLE_VALID) while the second set of filter coefficients (defined in the MODEM_CHFLT_RX2 properties) is effective after gear-switching. When the adaptive RX bandwidth feature is disabled, the first set of filter coefficients is used for the entire packet. This property sets the lower 8-bits of the 13th filter coefficient for the second set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX2_CHFLT_COEM0 property.
// MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - This property sets the lower 8-bits of the 12th filter coefficient for the second set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX2_CHFLT_COEM0 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - This property sets the lower 8-bits of the 11th filter coefficient for the second set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX2_CHFLT_COEM0 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - This property sets the lower 8-bits of the 10th filter coefficient for the second set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX2_CHFLT_COEM0 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - This property sets the lower 8-bits of the 9th filter coefficient for the second set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX2_CHFLT_COEM1 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_1 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - This property sets the lower 8-bits of the 8th filter coefficient for the second set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX2_CHFLT_COEM1 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
*/
#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE
/*
// Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
// Number of properties: 12
// Group ID: 21
// Start ID: 18
// Default values: 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00,
// Descriptions:
// MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - This property sets the lower 8-bits of the 7th filter coefficient for the second set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX2_CHFLT_COEM1 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_1 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - This property sets the lower 8-bits of the 6th filter coefficient for the second set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX2_CHFLT_COEM1 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_1 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - This property sets the lower 8-bits of the 5th filter coefficient for the second set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX2_CHFLT_COEM2 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - This property sets the lower 8-bits of the 4th filter coefficient for the second set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX2_CHFLT_COEM2 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - This property sets the lower 8-bits of the 3rd filter coefficient for the second set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX2_CHFLT_COEM2 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - This property sets the lower 8-bits of the 2nd filter coefficient for the second set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX2_CHFLT_COEM2 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - This property sets the lower 8-bits of the 1st filter coefficient for the second set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX2_CHFLT_COEM3 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - This property sets the lower 8-bits of the 0th filter coefficient for the second set of filter coefficients; the top two bits are packed into the MODEM_CHFLT_RX2_CHFLT_COEM3 property. Please refer to the text description for MODEM_CHFLT_RX1_CHFLT_COE13_7_0 for more details regarding programming of the channel selection filter tap coefficients.
// MODEM_CHFLT_RX2_CHFLT_COEM0 - There are 14 filter tap coefficient values; each value is a signed 10-bit value. The lower 8-bits of each coefficient are set in the MODEM_CHFLT_RX_CHFLT_COEXX properties, while the top two bits are packed into the MODEM_CHFLT_RX_CHFLT_COEMXX properties. This property contains the top two bits of the 13th through 10th filter coefficients for the second set of filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COEM1 - There are 14 filter tap coefficient values; each value is a signed 10-bit value. The lower 8-bits of each coefficient are set in the MODEM_CHFLT_RX_CHFLT_COEXX properties, while the top two bits are packed into the MODEM_CHFLT_RX_CHFLT_COEMXX properties. This property contains the top two bits of the 9th through 6th filter coefficients for the second set of filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COEM2 - There are 14 filter tap coefficient values; each value is a signed 10-bit value. The lower 8-bits of each coefficient are set in the MODEM_CHFLT_RX_CHFLT_COEXX properties, while the top two bits are packed into the MODEM_CHFLT_RX_CHFLT_COEMXX properties. This property contains the top two bits of the 5th through 2nd filter coefficients for the second set of filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COEM3 - There are 14 filter tap coefficient values; each value is a signed 10-bit value. The lower 8-bits of each coefficient are set in the MODEM_CHFLT_RX_CHFLT_COEXX properties, while the top two bits are packed into the MODEM_CHFLT_RX_CHFLT_COEMXX properties. This property contains the top two bits of the 1st through 0th filter coefficients for the second set of filter coefficients.
*/
#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00
/*
// Set properties: RF_PA_MODE_4
// Number of properties: 4
// Group ID: 22
// Start ID: 00
// Default values: 0x08, 0x7F, 0x00, 0x5D,
// Descriptions:
// PA_MODE - Specify PA mode and HPA/MPA groups.
// PA_PWR_LVL - Set the PA output power level with higher value as larger output power.
// PA_BIAS_CLKDUTY -
// PA_TC - Configuration control for PA power ramping in order to minimize switching spectrum noise. In (G)FSK mode, the values of TC and FSK_MOD_DLY should be programmed together so data modulation only occurs after the PA power ramping has been completed.
*/
#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D //PA操作模式和组，2组开，PA模式：Switch, for Square Wave or Class E，TX功率7F,发射占空比1/2，
//PA调制时间14US, 间歇时间:Ramp time = 20 s/(32-TC)
/*
// Set properties: RF_SYNTH_PFDCP_CPFF_7
// Number of properties: 7
// Group ID: 23
// Start ID: 00
// Default values: 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03,
// Descriptions:
// SYNTH_PFDCP_CPFF - The charge pump and loop filter in the PLL Synthesizer have two paths: an integral path and a feed-forward path. This property adjusts the charge pump gain (i.e., current) for the feed-forward path. The coding of the MSB (bit 5) of the CP_FF_CUR field is inverted. As a result, the minimum charge pump gain setting is obtained for a value of CP_FF_CUR=0x20, while CP_FF_CUR=0x00 corresponds to a mid-range charge pump gain setting and 0x1F corresponds to the maximum charge pump gain setting. The step size or resolution of the charge pump feed-forward current is in increments of 5 uA. Thus the range of values provided by the CP_FF_CUR field is from 0 uA to 315 uA. CP_FF_CUR_TEST is a test bit and is not recommended for general customer applications. The CP_FF_CUR_TEST bit is not binary-weighted with the CP_FF_CUR field but instead provides an additional 160 uA, when set. NOTE: the primary purpose of the SYNTH group of properties is to adjust the PLL loop bandwidth to a value appropriate for the selected data rate. Silicon Labs does not recommend modifying these properties away from the values suggested by the WDS Calculator.
// SYNTH_PFDCP_CPINT - The charge pump and loop filter in the PLL Synthesizer have two paths: an integral path and a feed-forward path. This property adjusts the charge pump gain (i.e., current) for the integral path. The coding of the MSB (bit 3) of the CP_INT_CUR field is inverted. As a result, the minimum charge pump gain setting is obtained for a value of CP_INT_CUR=0x08, while CP_INT_CUR=0x00 corresponds to a mid-range charge pump gain setting and 0x07 corresponds to the maximum charge pump gain setting. The step size or resolution of the charge pump feed-forward current is in increments of 5 uA. Thus the range of values provided by the CP_INT_CUR field is from 0 uA to 75 uA. NOTE: the primary purpose of the SYNTH group of properties is to adjust the PLL loop bandwidth to a value appropriate for the selected data rate. Silicon Labs does not recommend modifying these properties away from the values suggested by the WDS Calculator.
// SYNTH_VCO_KV - The charge pump, loop filter, and VCO tuning varactors in the PLL Synthesizer have two paths: an integral path and a feed-forward path. This property adjusts the gain scaling factors (Kv) for the tuning varactors in both the integral path and the feed-forward path. The adjustment of the gain factors is accomplished internally by switching in different number of varactor devices. NOTE: the primary purpose of the SYNTH group of properties is to adjust the PLL loop bandwidth to a value appropriate for the selected data rate. Silicon Labs does not recommend modifying these properties away from the values suggested by the WDS Calculator.
// SYNTH_LPFILT3 - The loop filter in the feed-forward path contains three lowpass filter poles: R1-C1, R2-C2, and R3-C3. The LPF_FF_R2 field adjusts the value of resistor R2, and thus adjusts the cutoff frequency of the R2-C2 lowpass filter pole. Additionally, the resistor R2 affects the DC gain of the transistor Gm stage in the feed-forward path. Increasing the value of R2 has the effect of increasing the feed-forward path gain. The value of R2 is in increments of 18 kOhm, ranging from a minimum value of 18 kOhm to a maximum of 144 kOhm. NOTE: the primary purpose of the SYNTH group of properties is to adjust the PLL loop bandwidth to a value appropriate for the selected data rate. Silicon Labs does not recommend modifying these properties away from the values suggested by the WDS Calculator.
// SYNTH_LPFILT2 - The loop filter in the feed-forward path contains three lowpass filter poles: R1-C1, R2-C2, and R3-C3. The LPF_FF_C2 field adjusts the value of capacitor C2, and thus adjusts the cutoff frequency of the R2-C2 lowpass filter pole. The value of C2 is in increments of 335 fF, ranging from a minimum value of 877 fF to a maximum of 11.25 pF. NOTE: the primary purpose of the SYNTH group of properties is to adjust the PLL loop bandwidth to a value appropriate for the selected data rate. Silicon Labs does not recommend modifying these properties away from the values suggested by the WDS Calculator.
// SYNTH_LPFILT1 - The loop filter in the feed-forward path contains three lowpass filter poles: R1-C1, R2-C2, and R3-C3. The LPF_FF_C3 field adjusts the value of capacitor C3, and thus adjusts the cutoff frequency of the R3-C3 lowpass filter pole. The value of resistor R3 is not adjustable and is fixed at R3=3.94 kOhm. The value of C3 is in increments of 1 pF, ranging from a minimum value of 9 pF to a maximum of 12 pF. The total value of capacitor C1 is determined by a 3-bit binary-weighted field LPF_FF_C1 in increments of 380 fF, and a 2-bit offset field LPF_FF_C1_CODE in increments of 1 pF, plus an additional fixed capacitance of 4.55 pF. Thus the total value of capacitor C1 may be described by the following equation: C1 = 4.55pF + 380fF*LPF_FF_C1 + 1pF*LPF_FF_C1_CODE The value of resistor R1 is not adjustable and is fixed at R1=9.86 kOhm. NOTE: the primary purpose of the SYNTH group of properties is to adjust the PLL loop bandwidth to a value appropriate for the selected data rate. Silicon Labs does not recommend modifying these properties away from the values suggested by the WDS Calculator.
// SYNTH_LPFILT0 - Bias current of the loop filter, 25 uA, 34 uA, 50 uA or 100 uA.
*/
#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
/*
// Set properties: RF_MATCH_VALUE_1_12
// Number of properties: 12
// Group ID: 30
// Start ID: 00
// Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
// Descriptions:
// MATCH_VALUE_1 -
// MATCH_MASK_1 -
// MATCH_CTRL_1 - Enable packet match processing and pattern 1 matches or not.
// MATCH_VALUE_2 -
// MATCH_MASK_2 -
// MATCH_CTRL_2 - Enable pattern 2 matches or not.
// MATCH_VALUE_3 -
// MATCH_MASK_3 -
// MATCH_CTRL_3 - Enable pattern 3 matches or not.
// MATCH_VALUE_4 -
// MATCH_MASK_4 -
// MATCH_CTRL_4 - Enable pattern 4 matches or not.
*/
#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
/*
// Set properties: RF_FREQ_CONTROL_INTE_8
// Number of properties: 8
// Group ID: 40
// Start ID: 00
// Default values: 0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF,
// Descriptions:
// FREQ_CONTROL_INTE - The total divide ratio for the Fractional-N PLL Synthesizer consists of an integer portion and a fractional portion. This property defines the integer divide number; the fractional divide value is specified in properties FREQ_CONTROL_FRAC_2, FREQ_CONTROL_FRAC_1, and FREQ_CONTROL_FRAC_0. The formula for calculating RF channel frequency as a function of integer and fractional divide values is as follows: The output divider value OUTDIV is configured as a function of the desired frequency band, and is specified in property MODEM_CLKGEN_BAND:BAND. The entire FC_FRAC word is 20-bits in length, but the MSB should always be set to 1, and thus the term FC_FRAC/2^19 will always be between 1 and 2 in value. As a result, the integer term FC_INTE should be reduced by 1. Example: a total desired divide ratio of N = 60.135 should be implemented as FC_INTE = 59, FC_FRAC/2^19 = 1.135. Modifying this property will have no effect until the chip exits from TX or RX state, and then re-enters the state.
// FREQ_CONTROL_FRAC_2 - Please refer to the text description for FREQ_CONTROL_INTE for more details regarding frequency calculation.
// FREQ_CONTROL_FRAC_1 - Please refer to the text description for FREQ_CONTROL_INTE for more details regarding frequency calculation.
// FREQ_CONTROL_FRAC_0 - Please refer to the text description for FREQ_CONTROL_INTE for more details regarding frequency calculation.
// FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - The EZ Frequency Programming method allows the user to control the frequency by selecting a desired channel number, given a base frequency and a channel step size. This property defines Byte 1 of the unsigned 16-bit channel step size value. The units of the FREQ_CONTROL_CHANNEL_STEP_SIZE_1/0 property are in increments of the LSB tuning resolution of the PLL Synthesizer, and are therefore a function of the crystal reference frequency and output frequency band. The formula for calculating the value of the FREQ_CONTROL_CHANNEL_STEP_SIZE property is given by the following equation: The base frequency is specified by the FREQ_CONTROL_INTE and FREQ_CONTROL_FRAC_2/1/0 properties. The channel number is specified by the CHANNEL parameter byte passed to the START_TX command. The commanded channel frequency is given by the formula:
// FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - The EZ Frequency Programming method allows the user to control the frequency by selecting a desired channel number, given a base frequency and a channel step size. This property defines Byte 0 of the unsigned 16-bit channel step size value. Please refer to the text description for FREQ_CONTROL_CHANNEL_STEP_SIZE_1 for more details regarding the channel step size function.
// FREQ_CONTROL_W_SIZE - The chip performs a calibration of the VCO at each new commanded frequency. This is accomplished by counting cycles of the VCO frequency and comparing to an expected target count value. The length of the window during which cycles of the VCO frequency are counted is specified by this property. The units are in cycles of the crystal reference frequency (e.g., 30 MHz clock periods). This property does not need to change as a function of crystal reference frequency; the chip automatically calculates the target VCO count value as a function of crystal reference frequency and thus this property may remain constant. Silicon Labs recommends setting this property always to 0x20.
// FREQ_CONTROL_VCOCNT_RX_ADJ - The chip performs a calibration of the VCO at each new commanded frequency. This is accomplished by counting cycles of the VCO frequency and comparing to an expected target count value. As the chip's default mode of operation uses a low-IF architecture with low-side Mixer injection, the RX LO must shift downwards in frequency during RX mode. The expected target count value changes as a result of this shift in frequency. This field is a signed value that represents the amount by which the target count value must be adjusted in RX mode.
*/
#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x38, 0x0D, 0xDD, 0xDD, 0x44, 0x44, 0x20, 0xFE //工作频段设置0X4000
// AUTOMATICALLY GENERATED CODE!
// DO NOT EDIT/MODIFY BELOW THIS LINE!
// --------------------------------------------
#ifndef FIRMWARE_LOAD_COMPILE
#define RADIO_CONFIGURATION_DATA_ARRAY { \
0x07, RF_POWER_UP, \
0x07, RF_GPIO_PIN_CFG, \
0x05, RF_GLOBAL_XO_TUNE_1, \
0x05, RF_GLOBAL_CONFIG_1, \
0x08, RF_INT_CTL_ENABLE_2, \
0x08, RF_FRR_CTL_A_MODE_4, \
0x0D, RF_PREAMBLE_TX_LENGTH_9, \
0x09, RF_SYNC_CONFIG_5, \
0x05, RF_PKT_CRC_CONFIG_1, \
0x05, RF_PKT_CONFIG1_1, \
0x07, RF_PKT_LEN_3, \
0x10, RF_PKT_FIELD_1_LENGTH_12_8_12, \
0x0C, RF_PKT_FIELD_4_LENGTH_12_8_8, \
0x10, RF_MODEM_MOD_TYPE_12, \
0x05, RF_MODEM_FREQ_DEV_0_1, \
0x0C, RF_MODEM_TX_RAMP_DELAY_8, \
0x0D, RF_MODEM_BCR_OSR_1_9, \
0x0B, RF_MODEM_AFC_GEAR_7, \
0x05, RF_MODEM_AGC_CONTROL_1, \
0x0D, RF_MODEM_AGC_WINDOW_SIZE_9, \
0x0F, RF_MODEM_OOK_CNT1_11, \
0x05, RF_MODEM_RSSI_COMP_1, \
0x05, RF_MODEM_CLKGEN_BAND_1, \
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
0x08, RF_PA_MODE_4, \
0x0B, RF_SYNTH_PFDCP_CPFF_7, \
0x10, RF_MATCH_VALUE_1_12, \
0x0C, RF_FREQ_CONTROL_INTE_8, \
0x00 \
}
#else
#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
#endif
// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 30000000L
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 0x00
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 0x10
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 0x01
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 0x1000
#define RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD_DEFAULT 0x42, 0x55, 0x54, 0x54, 0x4F, 0x4E, 0x31 // BUTTON1
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED 0x00
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE 0x00
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH { }
#ifndef RADIO_CONFIGURATION_DATA_ARRAY
#error "This property must be defined!"
#endif
#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ { RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT }
#endif
#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER { RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT }
#endif
#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH { RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT }
#endif
#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP { RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT }
#endif
#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET { RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT }
#endif
#ifndef RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD
#define RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD { RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD_DEFAULT }
#endif
#define RADIO_CONFIGURATION_DATA { \
Radio_Configuration_Data_Array, \
RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER, \
RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH, \
RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP, \
RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET, \
RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD \
}
#endif /* RADIO_CONFIG_H_ */
/************************************************************************************************************/
stm8s + si4463 寄存器配置
最新推荐文章于 2023-11-30 19:54:06 发布
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