Abstract
之前討論用硬體Verilog顯示8位數的七段顯示器，本文要討論在Nios II用軟體C語言控制8位數的七段顯示器。
Introduction
使用環境：Quartus II 7.2 SP1 + Nios II EDS 7.2 SP1 + DE2(Cyclone II EP2C35F627C6)
在(原創) 如何顯示8位數的七段顯示器? (IC Design) (Verilog) (DE2)曾經討論過用硬體Verilog顯示8位數的七段顯示器，今天剛好有需要想在Nios II從軟體C語言去控制七段顯示器，本來想自己寫一個custom component，後來發現友晶的NIOS II Reference Design已經寫好了，只要會『用』就好了。
Nios II的Reference Design放在DE2 CD中的\DE2_demonstrations\SOPC_Builder\Reference_Design\下，(或從http://www.terasic.com/downloads/cd-rom/de2/ 下載)，若你想自己從頭到尾自己由SOPC Builder建立，請參閱(原創) 如何自己用SOPC Builder建立一個能在DE2上跑μC/OS-II的Nios II系統? (IC Design) (DE2) (Quartus II) (Nios II) (SOPC Builder) (μC/OS-II)。
C語言 / hello_world.c
1
/*
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : hello_world.c
5 Compiler : Nios II gcc
6 Description : Demo how to display 7 seg.
7 Release : 04/27/2008 1.0
8 */
9 #include < stdio.h >
10 #include " system.h "
11 #include " basic_io.h "
12
13 int main() {
14 int i;
15 for (i = 0 ; i != 100 ; i ++ ) {
16 Sleep( 1 );
17 seg7_show(SEG7_DISPLAY_BASE, i);
18 }
19 }
20
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : hello_world.c
5 Compiler : Nios II gcc
6 Description : Demo how to display 7 seg.
7 Release : 04/27/2008 1.0
8 */
9 #include < stdio.h >
10 #include " system.h "
11 #include " basic_io.h "
12
13 int main() {
14 int i;
15 for (i = 0 ; i != 100 ; i ++ ) {
16 Sleep( 1 );
17 seg7_show(SEG7_DISPLAY_BASE, i);
18 }
19 }
20
你一定會問我，怎麼知道seg7_show()這個API可以在Nios II使用?我是在SEG7_LUT_8這個目錄下的inc\basic_io.h知道的，因為一個custom component一定會有一個include檔定義軟體能用的API。
C語言 / basic_io.h
1
#ifndef __basic_io_H__
2 #define __basic_io_H__
3
4 #include < io.h >
5 #include < stdio.h >
6 #include < unistd.h >
7 #include < stdlib.h >
8 #include " system.h "
9 #include " sys/alt_irq.h "
10
11 // for GPIO
12 #define inport(base) IORD(base, 0)
13 #define outport(base, data) IOWR(base, 0, data)
14 #define get_pio_dir(base) IORD(base, 1)
15 #define set_pio_dir(base, data) IOWR(base, 1, data)
16 #define get_pio_irq_mask(base) IORD(base, 2)
17 #define set_pio_irq_mask(base, data) IOWR(base, 2, data)
18 #define get_pio_edge_cap(base) IORD(base, 3)
19 #define set_pio_edge_cap(base, data) IOWR(base, 3, data)
20
21 // for SEG7 Display
22 #define seg7_show(base,data) IOWR(base, 0, data)
23
24 // for Time Delay
25 #define msleep(msec) usleep(1000*msec);
26 #define Sleep(sec) msleep(1000*sec);
27
28 #endif
2 #define __basic_io_H__
3
4 #include < io.h >
5 #include < stdio.h >
6 #include < unistd.h >
7 #include < stdlib.h >
8 #include " system.h "
9 #include " sys/alt_irq.h "
10
11 // for GPIO
12 #define inport(base) IORD(base, 0)
13 #define outport(base, data) IOWR(base, 0, data)
14 #define get_pio_dir(base) IORD(base, 1)
15 #define set_pio_dir(base, data) IOWR(base, 1, data)
16 #define get_pio_irq_mask(base) IORD(base, 2)
17 #define set_pio_irq_mask(base, data) IOWR(base, 2, data)
18 #define get_pio_edge_cap(base) IORD(base, 3)
19 #define set_pio_edge_cap(base, data) IOWR(base, 3, data)
20
21 // for SEG7 Display
22 #define seg7_show(base,data) IOWR(base, 0, data)
23
24 // for Time Delay
25 #define msleep(msec) usleep(1000*msec);
26 #define Sleep(sec) msleep(1000*sec);
27
28 #endif
21行
//
for SEG7 Display
#define seg7_show(base,data) IOWR(base, 0, data)
#define seg7_show(base,data) IOWR(base, 0, data)
我們發現了seg7_show()這個巨集，所以知道用這個巨集可以控制七段顯示器。
問題又來了，他要我們傳入七段顯示器的base address，我們要怎麼知道呢?
在SOPC Builder會分配每個component的base address，Nios II EDS在產生system library時，會將所有的address定義在\software\hello_world_0_syslib\Debug\system_description\system.h下。
C語言 / system.h
1
/*
system.h
2 *
3 * Machine generated for a CPU named "cpu_0" as defined in:
4 * c:\0Clare\DE2\switch_seg7_ip\software\hello_world_0_syslib\..\..\system_0.ptf
5 *
6 * Generated: 2008-04-27 00:14:19.203
7 *
8 */
9
10 #ifndef __SYSTEM_H_
11 #define __SYSTEM_H_
12
13 /*
14
15 DO NOT MODIFY THIS FILE
16
17 Changing this file will have subtle consequences
18 which will almost certainly lead to a nonfunctioning
19 system. If you do modify this file, be aware that your
20 changes will be overwritten and lost when this file
21 is generated again.
22
23 DO NOT MODIFY THIS FILE
24
25 */
26
27 /* *****************************************************************************
28 * *
29 * License Agreement *
30 * *
31 * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. *
32 * All rights reserved. *
33 * *
34 * Permission is hereby granted, free of charge, to any person obtaining a *
35 * copy of this software and associated documentation files (the "Software"), *
36 * to deal in the Software without restriction, including without limitation *
37 * the rights to use, copy, modify, merge, publish, distribute, sublicense, *
38 * and/or sell copies of the Software, and to permit persons to whom the *
39 * Software is furnished to do so, subject to the following conditions: *
40 * *
41 * The above copyright notice and this permission notice shall be included in *
42 * all copies or substantial portions of the Software. *
43 * *
44 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
45 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
46 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
47 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
48 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
49 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
50 * DEALINGS IN THE SOFTWARE. *
51 * *
52 * This agreement shall be governed in all respects by the laws of the State *
53 * of California and by the laws of the United States of America. *
54 * *
55 ***************************************************************************** */
56
57 /*
58 * system configuration
59 *
60 */
61
62 #define ALT_SYSTEM_NAME "system_0"
63 #define ALT_CPU_NAME "cpu_0"
64 #define ALT_CPU_ARCHITECTURE "altera_nios2"
65 #define ALT_DEVICE_FAMILY "CYCLONEII"
66 #define ALT_STDIN "/dev/jtag_uart_0"
67 #define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
68 #define ALT_STDIN_BASE 0x006810f0
69 #define ALT_STDIN_DEV jtag_uart_0
70 #define ALT_STDIN_PRESENT
71 #define ALT_STDOUT "/dev/jtag_uart_0"
72 #define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
73 #define ALT_STDOUT_BASE 0x006810f0
74 #define ALT_STDOUT_DEV jtag_uart_0
75 #define ALT_STDOUT_PRESENT
76 #define ALT_STDERR "/dev/jtag_uart_0"
77 #define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
78 #define ALT_STDERR_BASE 0x006810f0
79 #define ALT_STDERR_DEV jtag_uart_0
80 #define ALT_STDERR_PRESENT
81 #define ALT_CPU_FREQ 100000000
82 #define ALT_IRQ_BASE NULL
83
84 /*
85 * processor configuration
86 *
87 */
88
89 #define NIOS2_CPU_IMPLEMENTATION "fast"
90 #define NIOS2_BIG_ENDIAN 0
91
92 #define NIOS2_ICACHE_SIZE 4096
93 #define NIOS2_DCACHE_SIZE 2048
94 #define NIOS2_ICACHE_LINE_SIZE 32
95 #define NIOS2_ICACHE_LINE_SIZE_LOG2 5
96 #define NIOS2_DCACHE_LINE_SIZE 4
97 #define NIOS2_DCACHE_LINE_SIZE_LOG2 2
98 #define NIOS2_FLUSHDA_SUPPORTED
99
100 #define NIOS2_EXCEPTION_ADDR 0x00800020
101 #define NIOS2_RESET_ADDR 0x00000000
102 #define NIOS2_BREAK_ADDR 0x00680020
103
104 #define NIOS2_HAS_DEBUG_STUB
105
106 #define NIOS2_CPU_ID_SIZE 1
107 #define NIOS2_CPU_ID_VALUE 0
108
109 /*
110 * A define for each class of peripheral
111 *
112 */
113
114 #define __ALTERA_AVALON_TRI_STATE_BRIDGE
115 #define __ALTERA_AVALON_CFI_FLASH
116 #define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
117 #define __ALTERA_AVALON_EPCS_FLASH_CONTROLLER
118 #define __ALTERA_AVALON_JTAG_UART
119 #define __ALTERA_AVALON_UART
120 #define __ALTERA_AVALON_TIMER
121 #define __ALTERA_AVALON_LCD_16207
122 #define __ALTERA_AVALON_PIO
123 #define __SEG7_LUT_8
124 #define __SRAM_16BIT_512K
125 #define __DM9000A
126 #define __ISP1362
127 #define __BINARY_VGA_CONTROLLER
128 #define __AUDIO_DAC_FIFO
129
130 /*
131 * tri_state_bridge_0 configuration
132 *
133 */
134
135 #define TRI_STATE_BRIDGE_0_NAME "/dev/tri_state_bridge_0"
136 #define TRI_STATE_BRIDGE_0_TYPE "altera_avalon_tri_state_bridge"
137 #define ALT_MODULE_CLASS_tri_state_bridge_0 altera_avalon_tri_state_bridge
138
139 /*
140 * cfi_flash_0 configuration
141 *
142 */
143
144 #define CFI_FLASH_0_NAME "/dev/cfi_flash_0"
145 #define CFI_FLASH_0_TYPE "altera_avalon_cfi_flash"
146 #define CFI_FLASH_0_BASE 0x00000000
147 #define CFI_FLASH_0_SPAN 4194304
148 #define CFI_FLASH_0_SETUP_VALUE 40
149 #define CFI_FLASH_0_WAIT_VALUE 160
150 #define CFI_FLASH_0_HOLD_VALUE 40
151 #define CFI_FLASH_0_TIMING_UNITS "ns"
152 #define CFI_FLASH_0_UNIT_MULTIPLIER 1
153 #define CFI_FLASH_0_SIZE 4194304
154 #define ALT_MODULE_CLASS_cfi_flash_0 altera_avalon_cfi_flash
155
156 /*
157 * sdram_0 configuration
158 *
159 */
160
161 #define SDRAM_0_NAME "/dev/sdram_0"
162 #define SDRAM_0_TYPE "altera_avalon_new_sdram_controller"
163 #define SDRAM_0_BASE 0x00800000
164 #define SDRAM_0_SPAN 8388608
165 #define SDRAM_0_REGISTER_DATA_IN 1
166 #define SDRAM_0_SIM_MODEL_BASE 1
167 #define SDRAM_0_SDRAM_DATA_WIDTH 16
168 #define SDRAM_0_SDRAM_ADDR_WIDTH 12
169 #define SDRAM_0_SDRAM_ROW_WIDTH 12
170 #define SDRAM_0_SDRAM_COL_WIDTH 8
171 #define SDRAM_0_SDRAM_NUM_CHIPSELECTS 1
172 #define SDRAM_0_SDRAM_NUM_BANKS 4
173 #define SDRAM_0_REFRESH_PERIOD 15.625
174 #define SDRAM_0_POWERUP_DELAY 100.0
175 #define SDRAM_0_CAS_LATENCY 3
176 #define SDRAM_0_T_RFC 70.0
177 #define SDRAM_0_T_RP 20.0
178 #define SDRAM_0_T_MRD 3
179 #define SDRAM_0_T_RCD 20.0
180 #define SDRAM_0_T_AC 5.5
181 #define SDRAM_0_T_WR 14.0
182 #define SDRAM_0_INIT_REFRESH_COMMANDS 2
183 #define SDRAM_0_INIT_NOP_DELAY 0.0
184 #define SDRAM_0_SHARED_DATA 0
185 #define SDRAM_0_SDRAM_BANK_WIDTH 2
186 #define SDRAM_0_TRISTATE_BRIDGE_SLAVE ""
187 #define SDRAM_0_STARVATION_INDICATOR 0
188 #define SDRAM_0_IS_INITIALIZED 1
189 #define ALT_MODULE_CLASS_sdram_0 altera_avalon_new_sdram_controller
190
191 /*
192 * epcs_controller configuration
193 *
194 */
195
196 #define EPCS_CONTROLLER_NAME "/dev/epcs_controller"
197 #define EPCS_CONTROLLER_TYPE "altera_avalon_epcs_flash_controller"
198 #define EPCS_CONTROLLER_BASE 0x00680800
199 #define EPCS_CONTROLLER_SPAN 2048
200 #define EPCS_CONTROLLER_IRQ 0
201 #define EPCS_CONTROLLER_DATABITS 8
202 #define EPCS_CONTROLLER_TARGETCLOCK 20
203 #define EPCS_CONTROLLER_CLOCKUNITS "MHz"
204 #define EPCS_CONTROLLER_CLOCKMULT 1000000
205 #define EPCS_CONTROLLER_NUMSLAVES 1
206 #define EPCS_CONTROLLER_ISMASTER 1
207 #define EPCS_CONTROLLER_CLOCKPOLARITY 0
208 #define EPCS_CONTROLLER_CLOCKPHASE 0
209 #define EPCS_CONTROLLER_LSBFIRST 0
210 #define EPCS_CONTROLLER_EXTRADELAY 0
211 #define EPCS_CONTROLLER_TARGETSSDELAY 100
212 #define EPCS_CONTROLLER_DELAYUNITS "us"
213 #define EPCS_CONTROLLER_DELAYMULT "1e-006"
214 #define EPCS_CONTROLLER_PREFIX "epcs_"
215 #define EPCS_CONTROLLER_REGISTER_OFFSET 0x200
216 #define EPCS_CONTROLLER_USE_ASMI_ATOM 1
217 #define EPCS_CONTROLLER_CLOCKUNIT "kHz"
218 #define EPCS_CONTROLLER_DELAYUNIT "us"
219 #define ALT_MODULE_CLASS_epcs_controller altera_avalon_epcs_flash_controller
220
221 /*
222 * jtag_uart_0 configuration
223 *
224 */
225
226 #define JTAG_UART_0_NAME "/dev/jtag_uart_0"
227 #define JTAG_UART_0_TYPE "altera_avalon_jtag_uart"
228 #define JTAG_UART_0_BASE 0x006810f0
229 #define JTAG_UART_0_SPAN 8
230 #define JTAG_UART_0_IRQ 1
231 #define JTAG_UART_0_WRITE_DEPTH 64
232 #define JTAG_UART_0_READ_DEPTH 64
233 #define JTAG_UART_0_WRITE_THRESHOLD 8
234 #define JTAG_UART_0_READ_THRESHOLD 8
235 #define JTAG_UART_0_READ_CHAR_STREAM ""
236 #define JTAG_UART_0_SHOWASCII 1
237 #define JTAG_UART_0_READ_LE 0
238 #define JTAG_UART_0_WRITE_LE 0
239 #define JTAG_UART_0_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0
240 #define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart
241
242 /*
243 * uart_0 configuration
244 *
245 */
246
247 #define UART_0_NAME "/dev/uart_0"
248 #define UART_0_TYPE "altera_avalon_uart"
249 #define UART_0_BASE 0x00681000
250 #define UART_0_SPAN 32
251 #define UART_0_IRQ 2
252 #define UART_0_BAUD 115200
253 #define UART_0_DATA_BITS 8
254 #define UART_0_FIXED_BAUD 1
255 #define UART_0_PARITY 'N'
256 #define UART_0_STOP_BITS 1
257 #define UART_0_USE_CTS_RTS 0
258 #define UART_0_USE_EOP_REGISTER 0
259 #define UART_0_SIM_TRUE_BAUD 0
260 #define UART_0_SIM_CHAR_STREAM ""
261 #define UART_0_FREQ 100000000
262 #define ALT_MODULE_CLASS_uart_0 altera_avalon_uart
263
264 /*
265 * timer_0 configuration
266 *
267 */
268
269 #define TIMER_0_NAME "/dev/timer_0"
270 #define TIMER_0_TYPE "altera_avalon_timer"
271 #define TIMER_0_BASE 0x00681020
272 #define TIMER_0_SPAN 32
273 #define TIMER_0_IRQ 3
274 #define TIMER_0_ALWAYS_RUN 0
275 #define TIMER_0_FIXED_PERIOD 0
276 #define TIMER_0_SNAPSHOT 1
277 #define TIMER_0_PERIOD 1.0
278 #define TIMER_0_PERIOD_UNITS "ms"
279 #define TIMER_0_RESET_OUTPUT 0
280 #define TIMER_0_TIMEOUT_PULSE_OUTPUT 0
281 #define TIMER_0_LOAD_VALUE 99999
282 #define TIMER_0_MULT 0.001
283 #define TIMER_0_FREQ 100000000
284 #define ALT_MODULE_CLASS_timer_0 altera_avalon_timer
285
286 /*
287 * timer_1 configuration
288 *
289 */
290
291 #define TIMER_1_NAME "/dev/timer_1"
292 #define TIMER_1_TYPE "altera_avalon_timer"
293 #define TIMER_1_BASE 0x00681040
294 #define TIMER_1_SPAN 32
295 #define TIMER_1_IRQ 4
296 #define TIMER_1_ALWAYS_RUN 0
297 #define TIMER_1_FIXED_PERIOD 0
298 #define TIMER_1_SNAPSHOT 1
299 #define TIMER_1_PERIOD 1.0
300 #define TIMER_1_PERIOD_UNITS "ms"
301 #define TIMER_1_RESET_OUTPUT 0
302 #define TIMER_1_TIMEOUT_PULSE_OUTPUT 0
303 #define TIMER_1_LOAD_VALUE 99999
304 #define TIMER_1_MULT 0.001
305 #define TIMER_1_FREQ 100000000
306 #define ALT_MODULE_CLASS_timer_1 altera_avalon_timer
307
308 /*
309 * lcd_16207_0 configuration
310 *
311 */
312
313 #define LCD_16207_0_NAME "/dev/lcd_16207_0"
314 #define LCD_16207_0_TYPE "altera_avalon_lcd_16207"
315 #define LCD_16207_0_BASE 0x00681060
316 #define LCD_16207_0_SPAN 16
317 #define ALT_MODULE_CLASS_lcd_16207_0 altera_avalon_lcd_16207
318
319 /*
320 * led_red configuration
321 *
322 */
323
324 #define LED_RED_NAME "/dev/led_red"
325 #define LED_RED_TYPE "altera_avalon_pio"
326 #define LED_RED_BASE 0x00681070
327 #define LED_RED_SPAN 16
328 #define LED_RED_DO_TEST_BENCH_WIRING 0
329 #define LED_RED_DRIVEN_SIM_VALUE 0
330 #define LED_RED_HAS_TRI 0
331 #define LED_RED_HAS_OUT 1
332 #define LED_RED_HAS_IN 0
333 #define LED_RED_CAPTURE 0
334 #define LED_RED_DATA_WIDTH 18
335 #define LED_RED_EDGE_TYPE "NONE"
336 #define LED_RED_IRQ_TYPE "NONE"
337 #define LED_RED_BIT_CLEARING_EDGE_REGISTER 0
338 #define LED_RED_FREQ 100000000
339 #define ALT_MODULE_CLASS_led_red altera_avalon_pio
340
341 /*
342 * led_green configuration
343 *
344 */
345
346 #define LED_GREEN_NAME "/dev/led_green"
347 #define LED_GREEN_TYPE "altera_avalon_pio"
348 #define LED_GREEN_BASE 0x00681080
349 #define LED_GREEN_SPAN 16
350 #define LED_GREEN_DO_TEST_BENCH_WIRING 0
351 #define LED_GREEN_DRIVEN_SIM_VALUE 0
352 #define LED_GREEN_HAS_TRI 0
353 #define LED_GREEN_HAS_OUT 1
354 #define LED_GREEN_HAS_IN 0
355 #define LED_GREEN_CAPTURE 0
356 #define LED_GREEN_DATA_WIDTH 9
357 #define LED_GREEN_EDGE_TYPE "NONE"
358 #define LED_GREEN_IRQ_TYPE "NONE"
359 #define LED_GREEN_BIT_CLEARING_EDGE_REGISTER 0
360 #define LED_GREEN_FREQ 100000000
361 #define ALT_MODULE_CLASS_led_green altera_avalon_pio
362
363 /*
364 * button_pio configuration
365 *
366 */
367
368 #define BUTTON_PIO_NAME "/dev/button_pio"
369 #define BUTTON_PIO_TYPE "altera_avalon_pio"
370 #define BUTTON_PIO_BASE 0x00681090
371 #define BUTTON_PIO_SPAN 16
372 #define BUTTON_PIO_IRQ 5
373 #define BUTTON_PIO_DO_TEST_BENCH_WIRING 0
374 #define BUTTON_PIO_DRIVEN_SIM_VALUE 0
375 #define BUTTON_PIO_HAS_TRI 0
376 #define BUTTON_PIO_HAS_OUT 0
377 #define BUTTON_PIO_HAS_IN 1
378 #define BUTTON_PIO_CAPTURE 1
379 #define BUTTON_PIO_DATA_WIDTH 4
380 #define BUTTON_PIO_EDGE_TYPE "FALLING"
381 #define BUTTON_PIO_IRQ_TYPE "EDGE"
382 #define BUTTON_PIO_BIT_CLEARING_EDGE_REGISTER 0
383 #define BUTTON_PIO_FREQ 100000000
384 #define ALT_MODULE_CLASS_button_pio altera_avalon_pio
385
386 /*
387 * switch_pio configuration
388 *
389 */
390
391 #define SWITCH_PIO_NAME "/dev/switch_pio"
392 #define SWITCH_PIO_TYPE "altera_avalon_pio"
393 #define SWITCH_PIO_BASE 0x006810a0
394 #define SWITCH_PIO_SPAN 16
395 #define SWITCH_PIO_DO_TEST_BENCH_WIRING 0
396 #define SWITCH_PIO_DRIVEN_SIM_VALUE 0
397 #define SWITCH_PIO_HAS_TRI 0
398 #define SWITCH_PIO_HAS_OUT 0
399 #define SWITCH_PIO_HAS_IN 1
400 #define SWITCH_PIO_CAPTURE 0
401 #define SWITCH_PIO_DATA_WIDTH 18
402 #define SWITCH_PIO_EDGE_TYPE "NONE"
403 #define SWITCH_PIO_IRQ_TYPE "NONE"
404 #define SWITCH_PIO_BIT_CLEARING_EDGE_REGISTER 0
405 #define SWITCH_PIO_FREQ 100000000
406 #define ALT_MODULE_CLASS_switch_pio altera_avalon_pio
407
408 /*
409 * SEG7_Display configuration
410 *
411 */
412
413 #define SEG7_DISPLAY_NAME "/dev/SEG7_Display"
414 #define SEG7_DISPLAY_TYPE "seg7_lut_8"
415 #define SEG7_DISPLAY_BASE 0x00681100
416 #define SEG7_DISPLAY_SPAN 4
417 #define SEG7_DISPLAY_HDL_PARAMETERS ""
418 #define ALT_MODULE_CLASS_SEG7_Display seg7_lut_8
419
420 /*
421 * sram_0 configuration
422 *
423 */
424
425 #define SRAM_0_NAME "/dev/sram_0"
426 #define SRAM_0_TYPE "sram_16bit_512k"
427 #define SRAM_0_BASE 0x00600000
428 #define SRAM_0_SPAN 524288
429 #define SRAM_0_HDL_PARAMETERS ""
430 #define ALT_MODULE_CLASS_sram_0 sram_16bit_512k
431
432 /*
433 * DM9000A configuration
434 *
435 */
436
437 #define DM9000A_NAME "/dev/DM9000A"
438 #define DM9000A_TYPE "dm9000a"
439 #define DM9000A_BASE 0x006810f8
440 #define DM9000A_SPAN 8
441 #define DM9000A_IRQ 6
442 #define DM9000A_HDL_PARAMETERS ""
443 #define ALT_MODULE_CLASS_DM9000A dm9000a
444
445 /*
446 * ISP1362/avalon_slave_0 configuration
447 *
448 */
449
450 #define ISP1362_AVALON_SLAVE_0_NAME "/dev/ISP1362"
451 #define ISP1362_AVALON_SLAVE_0_TYPE "isp1362"
452 #define ISP1362_AVALON_SLAVE_0_BASE 0x006810b0
453 #define ISP1362_AVALON_SLAVE_0_SPAN 16
454 #define ISP1362_AVALON_SLAVE_0_IRQ 7
455 #define ISP1362_AVALON_SLAVE_0_HDL_PARAMETERS ""
456 #define ALT_MODULE_CLASS_ISP1362 isp1362
457
458 /*
459 * ISP1362/avalon_slave_1 configuration
460 *
461 */
462
463 #define ISP1362_AVALON_SLAVE_1_NAME "/dev/ISP1362"
464 #define ISP1362_AVALON_SLAVE_1_TYPE "isp1362"
465 #define ISP1362_AVALON_SLAVE_1_IRQ 8
466 #define ISP1362_AVALON_SLAVE_1_HDL_PARAMETERS ""
467 #define ALT_MODULE_CLASS_ISP1362 isp1362
468
469 /*
470 * VGA_0 configuration
471 *
472 */
473
474 #define VGA_0_NAME "/dev/VGA_0"
475 #define VGA_0_TYPE "binary_vga_controller"
476 #define VGA_0_BASE 0x00400000
477 #define VGA_0_SPAN 2097152
478 #define ALT_MODULE_CLASS_VGA_0 binary_vga_controller
479
480 /*
481 * Audio_0 configuration
482 *
483 */
484
485 #define AUDIO_0_NAME "/dev/Audio_0"
486 #define AUDIO_0_TYPE "audio_dac_fifo"
487 #define AUDIO_0_BASE 0x00681104
488 #define AUDIO_0_SPAN 4
489 #define ALT_MODULE_CLASS_Audio_0 audio_dac_fifo
490
491 /*
492 * SD_DAT configuration
493 *
494 */
495
496 #define SD_DAT_NAME "/dev/SD_DAT"
497 #define SD_DAT_TYPE "altera_avalon_pio"
498 #define SD_DAT_BASE 0x006810c0
499 #define SD_DAT_SPAN 16
500 #define SD_DAT_DO_TEST_BENCH_WIRING 0
501 #define SD_DAT_DRIVEN_SIM_VALUE 0
502 #define SD_DAT_HAS_TRI 1
503 #define SD_DAT_HAS_OUT 0
504 #define SD_DAT_HAS_IN 0
505 #define SD_DAT_CAPTURE 0
506 #define SD_DAT_DATA_WIDTH 1
507 #define SD_DAT_EDGE_TYPE "NONE"
508 #define SD_DAT_IRQ_TYPE "NONE"
509 #define SD_DAT_BIT_CLEARING_EDGE_REGISTER 0
510 #define SD_DAT_FREQ 100000000
511 #define ALT_MODULE_CLASS_SD_DAT altera_avalon_pio
512
513 /*
514 * SD_CMD configuration
515 *
516 */
517
518 #define SD_CMD_NAME "/dev/SD_CMD"
519 #define SD_CMD_TYPE "altera_avalon_pio"
520 #define SD_CMD_BASE 0x006810d0
521 #define SD_CMD_SPAN 16
522 #define SD_CMD_DO_TEST_BENCH_WIRING 0
523 #define SD_CMD_DRIVEN_SIM_VALUE 0
524 #define SD_CMD_HAS_TRI 1
525 #define SD_CMD_HAS_OUT 0
526 #define SD_CMD_HAS_IN 0
527 #define SD_CMD_CAPTURE 0
528 #define SD_CMD_DATA_WIDTH 1
529 #define SD_CMD_EDGE_TYPE "NONE"
530 #define SD_CMD_IRQ_TYPE "NONE"
531 #define SD_CMD_BIT_CLEARING_EDGE_REGISTER 0
532 #define SD_CMD_FREQ 100000000
533 #define ALT_MODULE_CLASS_SD_CMD altera_avalon_pio
534
535 /*
536 * SD_CLK configuration
537 *
538 */
539
540 #define SD_CLK_NAME "/dev/SD_CLK"
541 #define SD_CLK_TYPE "altera_avalon_pio"
542 #define SD_CLK_BASE 0x006810e0
543 #define SD_CLK_SPAN 16
544 #define SD_CLK_DO_TEST_BENCH_WIRING 0
545 #define SD_CLK_DRIVEN_SIM_VALUE 0
546 #define SD_CLK_HAS_TRI 0
547 #define SD_CLK_HAS_OUT 1
548 #define SD_CLK_HAS_IN 0
549 #define SD_CLK_CAPTURE 0
550 #define SD_CLK_DATA_WIDTH 1
551 #define SD_CLK_EDGE_TYPE "NONE"
552 #define SD_CLK_IRQ_TYPE "NONE"
553 #define SD_CLK_BIT_CLEARING_EDGE_REGISTER 0
554 #define SD_CLK_FREQ 100000000
555 #define ALT_MODULE_CLASS_SD_CLK altera_avalon_pio
556
557 /*
558 * system library configuration
559 *
560 */
561
562 #define ALT_MAX_FD 32
563 #define ALT_SYS_CLK TIMER_0
564 #define ALT_TIMESTAMP_CLK none
565
566 /*
567 * Devices associated with code sections.
568 *
569 */
570
571 #define ALT_TEXT_DEVICE SDRAM_0
572 #define ALT_RODATA_DEVICE SDRAM_0
573 #define ALT_RWDATA_DEVICE SDRAM_0
574 #define ALT_EXCEPTIONS_DEVICE SDRAM_0
575 #define ALT_RESET_DEVICE CFI_FLASH_0
576
577
578 #endif /* __SYSTEM_H_ */
2 *
3 * Machine generated for a CPU named "cpu_0" as defined in:
4 * c:\0Clare\DE2\switch_seg7_ip\software\hello_world_0_syslib\..\..\system_0.ptf
5 *
6 * Generated: 2008-04-27 00:14:19.203
7 *
8 */
9
10 #ifndef __SYSTEM_H_
11 #define __SYSTEM_H_
12
13 /*
14
15 DO NOT MODIFY THIS FILE
16
17 Changing this file will have subtle consequences
18 which will almost certainly lead to a nonfunctioning
19 system. If you do modify this file, be aware that your
20 changes will be overwritten and lost when this file
21 is generated again.
22
23 DO NOT MODIFY THIS FILE
24
25 */
26
27 /* *****************************************************************************
28 * *
29 * License Agreement *
30 * *
31 * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. *
32 * All rights reserved. *
33 * *
34 * Permission is hereby granted, free of charge, to any person obtaining a *
35 * copy of this software and associated documentation files (the "Software"), *
36 * to deal in the Software without restriction, including without limitation *
37 * the rights to use, copy, modify, merge, publish, distribute, sublicense, *
38 * and/or sell copies of the Software, and to permit persons to whom the *
39 * Software is furnished to do so, subject to the following conditions: *
40 * *
41 * The above copyright notice and this permission notice shall be included in *
42 * all copies or substantial portions of the Software. *
43 * *
44 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
45 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
46 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
47 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
48 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
49 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
50 * DEALINGS IN THE SOFTWARE. *
51 * *
52 * This agreement shall be governed in all respects by the laws of the State *
53 * of California and by the laws of the United States of America. *
54 * *
55 ***************************************************************************** */
56
57 /*
58 * system configuration
59 *
60 */
61
62 #define ALT_SYSTEM_NAME "system_0"
63 #define ALT_CPU_NAME "cpu_0"
64 #define ALT_CPU_ARCHITECTURE "altera_nios2"
65 #define ALT_DEVICE_FAMILY "CYCLONEII"
66 #define ALT_STDIN "/dev/jtag_uart_0"
67 #define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
68 #define ALT_STDIN_BASE 0x006810f0
69 #define ALT_STDIN_DEV jtag_uart_0
70 #define ALT_STDIN_PRESENT
71 #define ALT_STDOUT "/dev/jtag_uart_0"
72 #define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
73 #define ALT_STDOUT_BASE 0x006810f0
74 #define ALT_STDOUT_DEV jtag_uart_0
75 #define ALT_STDOUT_PRESENT
76 #define ALT_STDERR "/dev/jtag_uart_0"
77 #define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
78 #define ALT_STDERR_BASE 0x006810f0
79 #define ALT_STDERR_DEV jtag_uart_0
80 #define ALT_STDERR_PRESENT
81 #define ALT_CPU_FREQ 100000000
82 #define ALT_IRQ_BASE NULL
83
84 /*
85 * processor configuration
86 *
87 */
88
89 #define NIOS2_CPU_IMPLEMENTATION "fast"
90 #define NIOS2_BIG_ENDIAN 0
91
92 #define NIOS2_ICACHE_SIZE 4096
93 #define NIOS2_DCACHE_SIZE 2048
94 #define NIOS2_ICACHE_LINE_SIZE 32
95 #define NIOS2_ICACHE_LINE_SIZE_LOG2 5
96 #define NIOS2_DCACHE_LINE_SIZE 4
97 #define NIOS2_DCACHE_LINE_SIZE_LOG2 2
98 #define NIOS2_FLUSHDA_SUPPORTED
99
100 #define NIOS2_EXCEPTION_ADDR 0x00800020
101 #define NIOS2_RESET_ADDR 0x00000000
102 #define NIOS2_BREAK_ADDR 0x00680020
103
104 #define NIOS2_HAS_DEBUG_STUB
105
106 #define NIOS2_CPU_ID_SIZE 1
107 #define NIOS2_CPU_ID_VALUE 0
108
109 /*
110 * A define for each class of peripheral
111 *
112 */
113
114 #define __ALTERA_AVALON_TRI_STATE_BRIDGE
115 #define __ALTERA_AVALON_CFI_FLASH
116 #define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
117 #define __ALTERA_AVALON_EPCS_FLASH_CONTROLLER
118 #define __ALTERA_AVALON_JTAG_UART
119 #define __ALTERA_AVALON_UART
120 #define __ALTERA_AVALON_TIMER
121 #define __ALTERA_AVALON_LCD_16207
122 #define __ALTERA_AVALON_PIO
123 #define __SEG7_LUT_8
124 #define __SRAM_16BIT_512K
125 #define __DM9000A
126 #define __ISP1362
127 #define __BINARY_VGA_CONTROLLER
128 #define __AUDIO_DAC_FIFO
129
130 /*
131 * tri_state_bridge_0 configuration
132 *
133 */
134
135 #define TRI_STATE_BRIDGE_0_NAME "/dev/tri_state_bridge_0"
136 #define TRI_STATE_BRIDGE_0_TYPE "altera_avalon_tri_state_bridge"
137 #define ALT_MODULE_CLASS_tri_state_bridge_0 altera_avalon_tri_state_bridge
138
139 /*
140 * cfi_flash_0 configuration
141 *
142 */
143
144 #define CFI_FLASH_0_NAME "/dev/cfi_flash_0"
145 #define CFI_FLASH_0_TYPE "altera_avalon_cfi_flash"
146 #define CFI_FLASH_0_BASE 0x00000000
147 #define CFI_FLASH_0_SPAN 4194304
148 #define CFI_FLASH_0_SETUP_VALUE 40
149 #define CFI_FLASH_0_WAIT_VALUE 160
150 #define CFI_FLASH_0_HOLD_VALUE 40
151 #define CFI_FLASH_0_TIMING_UNITS "ns"
152 #define CFI_FLASH_0_UNIT_MULTIPLIER 1
153 #define CFI_FLASH_0_SIZE 4194304
154 #define ALT_MODULE_CLASS_cfi_flash_0 altera_avalon_cfi_flash
155
156 /*
157 * sdram_0 configuration
158 *
159 */
160
161 #define SDRAM_0_NAME "/dev/sdram_0"
162 #define SDRAM_0_TYPE "altera_avalon_new_sdram_controller"
163 #define SDRAM_0_BASE 0x00800000
164 #define SDRAM_0_SPAN 8388608
165 #define SDRAM_0_REGISTER_DATA_IN 1
166 #define SDRAM_0_SIM_MODEL_BASE 1
167 #define SDRAM_0_SDRAM_DATA_WIDTH 16
168 #define SDRAM_0_SDRAM_ADDR_WIDTH 12
169 #define SDRAM_0_SDRAM_ROW_WIDTH 12
170 #define SDRAM_0_SDRAM_COL_WIDTH 8
171 #define SDRAM_0_SDRAM_NUM_CHIPSELECTS 1
172 #define SDRAM_0_SDRAM_NUM_BANKS 4
173 #define SDRAM_0_REFRESH_PERIOD 15.625
174 #define SDRAM_0_POWERUP_DELAY 100.0
175 #define SDRAM_0_CAS_LATENCY 3
176 #define SDRAM_0_T_RFC 70.0
177 #define SDRAM_0_T_RP 20.0
178 #define SDRAM_0_T_MRD 3
179 #define SDRAM_0_T_RCD 20.0
180 #define SDRAM_0_T_AC 5.5
181 #define SDRAM_0_T_WR 14.0
182 #define SDRAM_0_INIT_REFRESH_COMMANDS 2
183 #define SDRAM_0_INIT_NOP_DELAY 0.0
184 #define SDRAM_0_SHARED_DATA 0
185 #define SDRAM_0_SDRAM_BANK_WIDTH 2
186 #define SDRAM_0_TRISTATE_BRIDGE_SLAVE ""
187 #define SDRAM_0_STARVATION_INDICATOR 0
188 #define SDRAM_0_IS_INITIALIZED 1
189 #define ALT_MODULE_CLASS_sdram_0 altera_avalon_new_sdram_controller
190
191 /*
192 * epcs_controller configuration
193 *
194 */
195
196 #define EPCS_CONTROLLER_NAME "/dev/epcs_controller"
197 #define EPCS_CONTROLLER_TYPE "altera_avalon_epcs_flash_controller"
198 #define EPCS_CONTROLLER_BASE 0x00680800
199 #define EPCS_CONTROLLER_SPAN 2048
200 #define EPCS_CONTROLLER_IRQ 0
201 #define EPCS_CONTROLLER_DATABITS 8
202 #define EPCS_CONTROLLER_TARGETCLOCK 20
203 #define EPCS_CONTROLLER_CLOCKUNITS "MHz"
204 #define EPCS_CONTROLLER_CLOCKMULT 1000000
205 #define EPCS_CONTROLLER_NUMSLAVES 1
206 #define EPCS_CONTROLLER_ISMASTER 1
207 #define EPCS_CONTROLLER_CLOCKPOLARITY 0
208 #define EPCS_CONTROLLER_CLOCKPHASE 0
209 #define EPCS_CONTROLLER_LSBFIRST 0
210 #define EPCS_CONTROLLER_EXTRADELAY 0
211 #define EPCS_CONTROLLER_TARGETSSDELAY 100
212 #define EPCS_CONTROLLER_DELAYUNITS "us"
213 #define EPCS_CONTROLLER_DELAYMULT "1e-006"
214 #define EPCS_CONTROLLER_PREFIX "epcs_"
215 #define EPCS_CONTROLLER_REGISTER_OFFSET 0x200
216 #define EPCS_CONTROLLER_USE_ASMI_ATOM 1
217 #define EPCS_CONTROLLER_CLOCKUNIT "kHz"
218 #define EPCS_CONTROLLER_DELAYUNIT "us"
219 #define ALT_MODULE_CLASS_epcs_controller altera_avalon_epcs_flash_controller
220
221 /*
222 * jtag_uart_0 configuration
223 *
224 */
225
226 #define JTAG_UART_0_NAME "/dev/jtag_uart_0"
227 #define JTAG_UART_0_TYPE "altera_avalon_jtag_uart"
228 #define JTAG_UART_0_BASE 0x006810f0
229 #define JTAG_UART_0_SPAN 8
230 #define JTAG_UART_0_IRQ 1
231 #define JTAG_UART_0_WRITE_DEPTH 64
232 #define JTAG_UART_0_READ_DEPTH 64
233 #define JTAG_UART_0_WRITE_THRESHOLD 8
234 #define JTAG_UART_0_READ_THRESHOLD 8
235 #define JTAG_UART_0_READ_CHAR_STREAM ""
236 #define JTAG_UART_0_SHOWASCII 1
237 #define JTAG_UART_0_READ_LE 0
238 #define JTAG_UART_0_WRITE_LE 0
239 #define JTAG_UART_0_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0
240 #define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart
241
242 /*
243 * uart_0 configuration
244 *
245 */
246
247 #define UART_0_NAME "/dev/uart_0"
248 #define UART_0_TYPE "altera_avalon_uart"
249 #define UART_0_BASE 0x00681000
250 #define UART_0_SPAN 32
251 #define UART_0_IRQ 2
252 #define UART_0_BAUD 115200
253 #define UART_0_DATA_BITS 8
254 #define UART_0_FIXED_BAUD 1
255 #define UART_0_PARITY 'N'
256 #define UART_0_STOP_BITS 1
257 #define UART_0_USE_CTS_RTS 0
258 #define UART_0_USE_EOP_REGISTER 0
259 #define UART_0_SIM_TRUE_BAUD 0
260 #define UART_0_SIM_CHAR_STREAM ""
261 #define UART_0_FREQ 100000000
262 #define ALT_MODULE_CLASS_uart_0 altera_avalon_uart
263
264 /*
265 * timer_0 configuration
266 *
267 */
268
269 #define TIMER_0_NAME "/dev/timer_0"
270 #define TIMER_0_TYPE "altera_avalon_timer"
271 #define TIMER_0_BASE 0x00681020
272 #define TIMER_0_SPAN 32
273 #define TIMER_0_IRQ 3
274 #define TIMER_0_ALWAYS_RUN 0
275 #define TIMER_0_FIXED_PERIOD 0
276 #define TIMER_0_SNAPSHOT 1
277 #define TIMER_0_PERIOD 1.0
278 #define TIMER_0_PERIOD_UNITS "ms"
279 #define TIMER_0_RESET_OUTPUT 0
280 #define TIMER_0_TIMEOUT_PULSE_OUTPUT 0
281 #define TIMER_0_LOAD_VALUE 99999
282 #define TIMER_0_MULT 0.001
283 #define TIMER_0_FREQ 100000000
284 #define ALT_MODULE_CLASS_timer_0 altera_avalon_timer
285
286 /*
287 * timer_1 configuration
288 *
289 */
290
291 #define TIMER_1_NAME "/dev/timer_1"
292 #define TIMER_1_TYPE "altera_avalon_timer"
293 #define TIMER_1_BASE 0x00681040
294 #define TIMER_1_SPAN 32
295 #define TIMER_1_IRQ 4
296 #define TIMER_1_ALWAYS_RUN 0
297 #define TIMER_1_FIXED_PERIOD 0
298 #define TIMER_1_SNAPSHOT 1
299 #define TIMER_1_PERIOD 1.0
300 #define TIMER_1_PERIOD_UNITS "ms"
301 #define TIMER_1_RESET_OUTPUT 0
302 #define TIMER_1_TIMEOUT_PULSE_OUTPUT 0
303 #define TIMER_1_LOAD_VALUE 99999
304 #define TIMER_1_MULT 0.001
305 #define TIMER_1_FREQ 100000000
306 #define ALT_MODULE_CLASS_timer_1 altera_avalon_timer
307
308 /*
309 * lcd_16207_0 configuration
310 *
311 */
312
313 #define LCD_16207_0_NAME "/dev/lcd_16207_0"
314 #define LCD_16207_0_TYPE "altera_avalon_lcd_16207"
315 #define LCD_16207_0_BASE 0x00681060
316 #define LCD_16207_0_SPAN 16
317 #define ALT_MODULE_CLASS_lcd_16207_0 altera_avalon_lcd_16207
318
319 /*
320 * led_red configuration
321 *
322 */
323
324 #define LED_RED_NAME "/dev/led_red"
325 #define LED_RED_TYPE "altera_avalon_pio"
326 #define LED_RED_BASE 0x00681070
327 #define LED_RED_SPAN 16
328 #define LED_RED_DO_TEST_BENCH_WIRING 0
329 #define LED_RED_DRIVEN_SIM_VALUE 0
330 #define LED_RED_HAS_TRI 0
331 #define LED_RED_HAS_OUT 1
332 #define LED_RED_HAS_IN 0
333 #define LED_RED_CAPTURE 0
334 #define LED_RED_DATA_WIDTH 18
335 #define LED_RED_EDGE_TYPE "NONE"
336 #define LED_RED_IRQ_TYPE "NONE"
337 #define LED_RED_BIT_CLEARING_EDGE_REGISTER 0
338 #define LED_RED_FREQ 100000000
339 #define ALT_MODULE_CLASS_led_red altera_avalon_pio
340
341 /*
342 * led_green configuration
343 *
344 */
345
346 #define LED_GREEN_NAME "/dev/led_green"
347 #define LED_GREEN_TYPE "altera_avalon_pio"
348 #define LED_GREEN_BASE 0x00681080
349 #define LED_GREEN_SPAN 16
350 #define LED_GREEN_DO_TEST_BENCH_WIRING 0
351 #define LED_GREEN_DRIVEN_SIM_VALUE 0
352 #define LED_GREEN_HAS_TRI 0
353 #define LED_GREEN_HAS_OUT 1
354 #define LED_GREEN_HAS_IN 0
355 #define LED_GREEN_CAPTURE 0
356 #define LED_GREEN_DATA_WIDTH 9
357 #define LED_GREEN_EDGE_TYPE "NONE"
358 #define LED_GREEN_IRQ_TYPE "NONE"
359 #define LED_GREEN_BIT_CLEARING_EDGE_REGISTER 0
360 #define LED_GREEN_FREQ 100000000
361 #define ALT_MODULE_CLASS_led_green altera_avalon_pio
362
363 /*
364 * button_pio configuration
365 *
366 */
367
368 #define BUTTON_PIO_NAME "/dev/button_pio"
369 #define BUTTON_PIO_TYPE "altera_avalon_pio"
370 #define BUTTON_PIO_BASE 0x00681090
371 #define BUTTON_PIO_SPAN 16
372 #define BUTTON_PIO_IRQ 5
373 #define BUTTON_PIO_DO_TEST_BENCH_WIRING 0
374 #define BUTTON_PIO_DRIVEN_SIM_VALUE 0
375 #define BUTTON_PIO_HAS_TRI 0
376 #define BUTTON_PIO_HAS_OUT 0
377 #define BUTTON_PIO_HAS_IN 1
378 #define BUTTON_PIO_CAPTURE 1
379 #define BUTTON_PIO_DATA_WIDTH 4
380 #define BUTTON_PIO_EDGE_TYPE "FALLING"
381 #define BUTTON_PIO_IRQ_TYPE "EDGE"
382 #define BUTTON_PIO_BIT_CLEARING_EDGE_REGISTER 0
383 #define BUTTON_PIO_FREQ 100000000
384 #define ALT_MODULE_CLASS_button_pio altera_avalon_pio
385
386 /*
387 * switch_pio configuration
388 *
389 */
390
391 #define SWITCH_PIO_NAME "/dev/switch_pio"
392 #define SWITCH_PIO_TYPE "altera_avalon_pio"
393 #define SWITCH_PIO_BASE 0x006810a0
394 #define SWITCH_PIO_SPAN 16
395 #define SWITCH_PIO_DO_TEST_BENCH_WIRING 0
396 #define SWITCH_PIO_DRIVEN_SIM_VALUE 0
397 #define SWITCH_PIO_HAS_TRI 0
398 #define SWITCH_PIO_HAS_OUT 0
399 #define SWITCH_PIO_HAS_IN 1
400 #define SWITCH_PIO_CAPTURE 0
401 #define SWITCH_PIO_DATA_WIDTH 18
402 #define SWITCH_PIO_EDGE_TYPE "NONE"
403 #define SWITCH_PIO_IRQ_TYPE "NONE"
404 #define SWITCH_PIO_BIT_CLEARING_EDGE_REGISTER 0
405 #define SWITCH_PIO_FREQ 100000000
406 #define ALT_MODULE_CLASS_switch_pio altera_avalon_pio
407
408 /*
409 * SEG7_Display configuration
410 *
411 */
412
413 #define SEG7_DISPLAY_NAME "/dev/SEG7_Display"
414 #define SEG7_DISPLAY_TYPE "seg7_lut_8"
415 #define SEG7_DISPLAY_BASE 0x00681100
416 #define SEG7_DISPLAY_SPAN 4
417 #define SEG7_DISPLAY_HDL_PARAMETERS ""
418 #define ALT_MODULE_CLASS_SEG7_Display seg7_lut_8
419
420 /*
421 * sram_0 configuration
422 *
423 */
424
425 #define SRAM_0_NAME "/dev/sram_0"
426 #define SRAM_0_TYPE "sram_16bit_512k"
427 #define SRAM_0_BASE 0x00600000
428 #define SRAM_0_SPAN 524288
429 #define SRAM_0_HDL_PARAMETERS ""
430 #define ALT_MODULE_CLASS_sram_0 sram_16bit_512k
431
432 /*
433 * DM9000A configuration
434 *
435 */
436
437 #define DM9000A_NAME "/dev/DM9000A"
438 #define DM9000A_TYPE "dm9000a"
439 #define DM9000A_BASE 0x006810f8
440 #define DM9000A_SPAN 8
441 #define DM9000A_IRQ 6
442 #define DM9000A_HDL_PARAMETERS ""
443 #define ALT_MODULE_CLASS_DM9000A dm9000a
444
445 /*
446 * ISP1362/avalon_slave_0 configuration
447 *
448 */
449
450 #define ISP1362_AVALON_SLAVE_0_NAME "/dev/ISP1362"
451 #define ISP1362_AVALON_SLAVE_0_TYPE "isp1362"
452 #define ISP1362_AVALON_SLAVE_0_BASE 0x006810b0
453 #define ISP1362_AVALON_SLAVE_0_SPAN 16
454 #define ISP1362_AVALON_SLAVE_0_IRQ 7
455 #define ISP1362_AVALON_SLAVE_0_HDL_PARAMETERS ""
456 #define ALT_MODULE_CLASS_ISP1362 isp1362
457
458 /*
459 * ISP1362/avalon_slave_1 configuration
460 *
461 */
462
463 #define ISP1362_AVALON_SLAVE_1_NAME "/dev/ISP1362"
464 #define ISP1362_AVALON_SLAVE_1_TYPE "isp1362"
465 #define ISP1362_AVALON_SLAVE_1_IRQ 8
466 #define ISP1362_AVALON_SLAVE_1_HDL_PARAMETERS ""
467 #define ALT_MODULE_CLASS_ISP1362 isp1362
468
469 /*
470 * VGA_0 configuration
471 *
472 */
473
474 #define VGA_0_NAME "/dev/VGA_0"
475 #define VGA_0_TYPE "binary_vga_controller"
476 #define VGA_0_BASE 0x00400000
477 #define VGA_0_SPAN 2097152
478 #define ALT_MODULE_CLASS_VGA_0 binary_vga_controller
479
480 /*
481 * Audio_0 configuration
482 *
483 */
484
485 #define AUDIO_0_NAME "/dev/Audio_0"
486 #define AUDIO_0_TYPE "audio_dac_fifo"
487 #define AUDIO_0_BASE 0x00681104
488 #define AUDIO_0_SPAN 4
489 #define ALT_MODULE_CLASS_Audio_0 audio_dac_fifo
490
491 /*
492 * SD_DAT configuration
493 *
494 */
495
496 #define SD_DAT_NAME "/dev/SD_DAT"
497 #define SD_DAT_TYPE "altera_avalon_pio"
498 #define SD_DAT_BASE 0x006810c0
499 #define SD_DAT_SPAN 16
500 #define SD_DAT_DO_TEST_BENCH_WIRING 0
501 #define SD_DAT_DRIVEN_SIM_VALUE 0
502 #define SD_DAT_HAS_TRI 1
503 #define SD_DAT_HAS_OUT 0
504 #define SD_DAT_HAS_IN 0
505 #define SD_DAT_CAPTURE 0
506 #define SD_DAT_DATA_WIDTH 1
507 #define SD_DAT_EDGE_TYPE "NONE"
508 #define SD_DAT_IRQ_TYPE "NONE"
509 #define SD_DAT_BIT_CLEARING_EDGE_REGISTER 0
510 #define SD_DAT_FREQ 100000000
511 #define ALT_MODULE_CLASS_SD_DAT altera_avalon_pio
512
513 /*
514 * SD_CMD configuration
515 *
516 */
517
518 #define SD_CMD_NAME "/dev/SD_CMD"
519 #define SD_CMD_TYPE "altera_avalon_pio"
520 #define SD_CMD_BASE 0x006810d0
521 #define SD_CMD_SPAN 16
522 #define SD_CMD_DO_TEST_BENCH_WIRING 0
523 #define SD_CMD_DRIVEN_SIM_VALUE 0
524 #define SD_CMD_HAS_TRI 1
525 #define SD_CMD_HAS_OUT 0
526 #define SD_CMD_HAS_IN 0
527 #define SD_CMD_CAPTURE 0
528 #define SD_CMD_DATA_WIDTH 1
529 #define SD_CMD_EDGE_TYPE "NONE"
530 #define SD_CMD_IRQ_TYPE "NONE"
531 #define SD_CMD_BIT_CLEARING_EDGE_REGISTER 0
532 #define SD_CMD_FREQ 100000000
533 #define ALT_MODULE_CLASS_SD_CMD altera_avalon_pio
534
535 /*
536 * SD_CLK configuration
537 *
538 */
539
540 #define SD_CLK_NAME "/dev/SD_CLK"
541 #define SD_CLK_TYPE "altera_avalon_pio"
542 #define SD_CLK_BASE 0x006810e0
543 #define SD_CLK_SPAN 16
544 #define SD_CLK_DO_TEST_BENCH_WIRING 0
545 #define SD_CLK_DRIVEN_SIM_VALUE 0
546 #define SD_CLK_HAS_TRI 0
547 #define SD_CLK_HAS_OUT 1
548 #define SD_CLK_HAS_IN 0
549 #define SD_CLK_CAPTURE 0
550 #define SD_CLK_DATA_WIDTH 1
551 #define SD_CLK_EDGE_TYPE "NONE"
552 #define SD_CLK_IRQ_TYPE "NONE"
553 #define SD_CLK_BIT_CLEARING_EDGE_REGISTER 0
554 #define SD_CLK_FREQ 100000000
555 #define ALT_MODULE_CLASS_SD_CLK altera_avalon_pio
556
557 /*
558 * system library configuration
559 *
560 */
561
562 #define ALT_MAX_FD 32
563 #define ALT_SYS_CLK TIMER_0
564 #define ALT_TIMESTAMP_CLK none
565
566 /*
567 * Devices associated with code sections.
568 *
569 */
570
571 #define ALT_TEXT_DEVICE SDRAM_0
572 #define ALT_RODATA_DEVICE SDRAM_0
573 #define ALT_RWDATA_DEVICE SDRAM_0
574 #define ALT_EXCEPTIONS_DEVICE SDRAM_0
575 #define ALT_RESET_DEVICE CFI_FLASH_0
576
577
578 #endif /* __SYSTEM_H_ */
413行
#define
SEG7_DISPLAY_NAME "/dev/SEG7_Display"
#define SEG7_DISPLAY_TYPE "seg7_lut_8"
#define SEG7_DISPLAY_BASE 0x00681100
#define SEG7_DISPLAY_SPAN 4
#define SEG7_DISPLAY_HDL_PARAMETERS ""
#define ALT_MODULE_CLASS_SEG7_Display seg7_lut_8
#define SEG7_DISPLAY_TYPE "seg7_lut_8"
#define SEG7_DISPLAY_BASE 0x00681100
#define SEG7_DISPLAY_SPAN 4
#define SEG7_DISPLAY_HDL_PARAMETERS ""
#define ALT_MODULE_CLASS_SEG7_Display seg7_lut_8
我們發現和七段顯示器相關的巨集定義都在這，其中SEG7_DISPLAY_BASE定義的就是其base address，這也是為什麼在hello_world.c的第9行
#include
<
stdio.h
>
#include " system.h "
#include " basic_io.h "
#include " system.h "
#include " basic_io.h "
要include system.h和basic_io.h的原因。
完整程式碼下載
switch_seg7_sw.7z
Conclusion
本文的目的不只是在討論如何在Nios II用C語言去控制七段顯示器，重點是學習將來遇到新的controller時，要怎麼在軟體C語言中使用，如何到.h檔中找API?如何到system.h找定義base address的巨集?這才是更重要的。
See Also
(原創) 如何顯示8位數的七段顯示器? (IC Design) (Verilog) (DE2)
(原創) 如何自己用SOPC Builder建立一個能在DE2上跑μC/OS-II的Nios II系統? (IC Design) (DE2) (Quartus II) (Nios II) (SOPC Builder) (μC/OS-II)
(原創) 如何在Nios II使用16x2字元液晶顯示器? (IC Design) (DE2) (Nios II)
(原創) 如何以10進位顯示8位數的七段顯示器? (SOC) (Verilog) (DE2)
(原創) 如何在Nios II顯示8位數的七段顯示器? (SOC) (Nios II) (SOPC Builder) (DE2-70)
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