1. A method for manufacturing a thin film transistor array substrate including gate and data lines intersecting with each other to define a plurality of pixel areas, comprising:
forming, on the substrate, the gate lines and gate electrodes respectively branched from corresponding ones of the gate lines to the pixel areas;
forming, over the substrate, a gate insulating film to cover the gate lines and the gate electrodes;
forming, on the gate insulating film, active layers to overlap with the gate electrodes, respectively;
forming, over the gate insulating film, a multilayer structure including at least one first metal layer and a second metal layer made of copper (Cu);
forming, on the multilayer structure, a first mask layer including first mask areas having a first height and second mask areas having a second height which is lower than the first height, the first mask areas respectively corresponding to the data lines, the second mask areas respectively corresponding to electrode patterns, each electrode pattern corresponding to a source electrode, a drain electrode, and a channel area of the active layer, and the channel area of the active layer corresponding to a space between the source electrode and the drain electrode;
patterning the multilayer structure under condition that the first mask layer has been formed, thereby forming the data lines constituted by the multilayer structure;
ashing the first mask layer such that the first mask areas have a third height lower tha
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