Abstract
本文使用Verilog在DE2-70實現real time的binary image。
Introduction
使用環境：Quartus II 8.0 + DE2-70 (Cyclone II EP2C70F896C6N) + TRDB-D5M + TRDB-LTM
Binary image是所有電腦視覺演算法的基礎，本文提供一個Binary module，供後續研究各種影像處理演算法使用。
系統架構圖
Binary Image Module
Binary.v / Verilog
1
/*
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : Binary.v
5 Compiler : Quartus II 8.0
6 Description : Demo how to implement binary image in Verilog
7 Release : 09/20/2008 1.0
8 */
9
10 module Binary (
11 input iCLK,
12 input iRST_N,
13 input [ 9 : 0 ] iTHRESHOLD,
14 input iDVAL,
15 input [ 9 : 0 ] iDATA,
16 output reg oDVAL,
17 output reg [ 9 : 0 ] oDATA
18 );
19
20 always @( posedge iCLK, negedge iRST_N) begin
21 if ( ! iRST_N) begin
22 oDVAL <= 1 ' b0;
23 oDATA <= 10 ' h0;
24 end
25 else begin
26 oDVAL <= iDVAL;
27
28 if (iDVAL)
29 oDATA <= (iDATA > iTHRESHOLD) ? 1023 : 0 ;
30 else
31 oDATA <= 10 ' b0;
32 end
33 end
34
35 endmodule
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : Binary.v
5 Compiler : Quartus II 8.0
6 Description : Demo how to implement binary image in Verilog
7 Release : 09/20/2008 1.0
8 */
9
10 module Binary (
11 input iCLK,
12 input iRST_N,
13 input [ 9 : 0 ] iTHRESHOLD,
14 input iDVAL,
15 input [ 9 : 0 ] iDATA,
16 output reg oDVAL,
17 output reg [ 9 : 0 ] oDATA
18 );
19
20 always @( posedge iCLK, negedge iRST_N) begin
21 if ( ! iRST_N) begin
22 oDVAL <= 1 ' b0;
23 oDATA <= 10 ' h0;
24 end
25 else begin
26 oDVAL <= iDVAL;
27
28 if (iDVAL)
29 oDATA <= (iDATA > iTHRESHOLD) ? 1023 : 0 ;
30 else
31 oDATA <= 10 ' b0;
32 end
33 end
34
35 endmodule
在DE2-70上實現
使用友晶科技DE2_70_D5M_LTM範例加以修改
DE2_70.v / Verilog
1
/*
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : DE2_70.v
5 Compiler : Quartus II 8.0
6 Description : Demo how to implement binary image on DE2-70
7 Release : 09/20/2008 1.0
8 */
9
10 module DE2_70 (
11 Clock Input
12 input iCLK_28, // 28.63636 MHz
13 input iCLK_50, // 50 MHz
14 input iCLK_50_2, // 50 MHz
15 input iCLK_50_3, // 50 MHz
16 input iCLK_50_4, // 50 MHz
17 input iEXT_CLOCK, // External Clock
18 Push Button
19 input [ 3 : 0 ] iKEY, // Pushbutton[3:0]
20 DPDT Switch
21 input [ 17 : 0 ] iSW, // Toggle Switch[17:0]
22 7-SEG Dispaly
23 output [ 6 : 0 ] oHEX0_D, // Seven Segment Digit 0
24 output oHEX0_DP, // Seven Segment Digit 0 decimal point
25 output [ 6 : 0 ] oHEX1_D, // Seven Segment Digit 1
26 output oHEX1_DP, // Seven Segment Digit 1 decimal point
27 output [ 6 : 0 ] oHEX2_D, // Seven Segment Digit 2
28 output oHEX2_DP, // Seven Segment Digit 2 decimal point
29 output [ 6 : 0 ] oHEX3_D, // Seven Segment Digit 3
30 output oHEX3_DP, // Seven Segment Digit 3 decimal point
31 output [ 6 : 0 ] oHEX4_D, // Seven Segment Digit 4
32 output oHEX4_DP, // Seven Segment Digit 4 decimal point
33 output [ 6 : 0 ] oHEX5_D, // Seven Segment Digit 5
34 output oHEX5_DP, // Seven Segment Digit 5 decimal point
35 output [ 6 : 0 ] oHEX6_D, // Seven Segment Digit 6
36 output oHEX6_DP, // Seven Segment Digit 6 decimal point
37 output [ 6 : 0 ] oHEX7_D, // Seven Segment Digit 7
38 output oHEX7_DP, // Seven Segment Digit 7 decimal point
39 /// / LED /// /
40 output [ 8 : 0 ] oLEDG, // LED Green[8:0]
41 output [ 17 : 0 ] oLEDR, // LED Red[17:0]
42 /// / UART /// /
43 output oUART_TXD, // UART Transmitter
44 input iUART_RXD, // UART Receiver
45 output oUART_CTS, // UART Clear To Send
46 input iUART_RTS, // UART Requst To Send
47 /// / IRDA /// /
48 output oIRDA_TXD, // IRDA Transmitter
49 input iIRDA_RXD, // IRDA Receiver
50 / // SDRAM Interface
51 inout [ 31 : 0 ] DRAM_DQ, // SDRAM Data bus 32 Bits
52 output [ 12 : 0 ] oDRAM0_A, // SDRAM0 Address bus 13 Bits
53 output [ 12 : 0 ] oDRAM1_A, // SDRAM1 Address bus 13 Bits
54 output oDRAM0_LDQM0, // SDRAM0 Low-byte Data Mask
55 output oDRAM1_LDQM0, // SDRAM1 Low-byte Data Mask
56 output oDRAM0_UDQM1, // SDRAM0 High-byte Data Mask
57 output oDRAM1_UDQM1, // SDRAM1 High-byte Data Mask
58 output oDRAM0_WE_N, // SDRAM0 Write Enable
59 output oDRAM1_WE_N, // SDRAM1 Write Enable
60 output oDRAM0_CAS_N, // SDRAM0 Column Address Strobe
61 output oDRAM1_CAS_N, // SDRAM1 Column Address Strobe
62 output oDRAM0_RAS_N, // SDRAM0 Row Address Strobe
63 output oDRAM1_RAS_N, // SDRAM1 Row Address Strobe
64 output oDRAM0_CS_N, // SDRAM0 Chip Select
65 output oDRAM1_CS_N, // SDRAM1 Chip Select
66 output [ 1 : 0 ] oDRAM0_BA, // SDRAM0 Bank Address
67 output [ 1 : 0 ] oDRAM1_BA, // SDRAM1 Bank Address
68 output oDRAM0_CLK, // SDRAM0 Clock
69 output oDRAM1_CLK, // SDRAM1 Clock
70 output oDRAM0_CKE, // SDRAM0 Clock Enable
71 output oDRAM1_CKE, // SDRAM1 Clock Enable
72 Flash Interface
73 inout [ 14 : 0 ] FLASH_DQ, // FLASH Data bus 15 Bits (0 to 14)
74 inout FLASH_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1
75 output [ 21 : 0 ] oFLASH_A, // FLASH Address bus 26 Bits
76 output oFLASH_WE_N, // FLASH Write Enable
77 output oFLASH_RST_N, // FLASH Reset
78 output oFLASH_WP_N, // FLASH Write Protect /Programming Acceleration
79 input iFLASH_RY_N, // FLASH Ready/Busy output
80 output oFLASH_BYTE_N, // FLASH Byte/Word Mode Configuration
81 output oFLASH_OE_N, // FLASH Output Enable
82 output oFLASH_CE_N, // FLASH Chip Enable
83 SRAM Interface
84 inout [ 31 : 0 ] SRAM_DQ, // SRAM Data Bus 32 Bits
85 inout [ 3 : 0 ] SRAM_DPA, // SRAM Parity Data Bus
86 output [ 18 : 0 ] oSRAM_A, // SRAM Address bus 21 Bits
87 output oSRAM_ADSC_N, // SRAM Controller Address Status
88 output oSRAM_ADSP_N, // SRAM Processor Address Status
89 output oSRAM_ADV_N, // SRAM Burst Address Advance
90 output [ 3 : 0 ] oSRAM_BE_N, // SRAM Byte Write Enable
91 output oSRAM_CE1_N, // SRAM Chip Enable
92 output oSRAM_CE2, // SRAM Chip Enable
93 output oSRAM_CE3_N, // SRAM Chip Enable
94 output oSRAM_CLK, // SRAM Clock
95 output oSRAM_GW_N, // SRAM Global Write Enable
96 output oSRAM_OE_N, // SRAM Output Enable
97 output oSRAM_WE_N, // SRAM Write Enable
98 // // ISP1362 Interface
99 inout [ 15 : 0 ] OTG_D, // ISP1362 Data bus 16 Bits
100 output [ 1 : 0 ] oOTG_A, // ISP1362 Address 2 Bits
101 output oOTG_CS_N, // ISP1362 Chip Select
102 output oOTG_OE_N, // ISP1362 Read
103 output oOTG_WE_N, // ISP1362 Write
104 output oOTG_RESET_N, // ISP1362 Reset
105 inout OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
106 inout OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
107 input iOTG_INT0, // ISP1362 Interrupt 0
108 input iOTG_INT1, // ISP1362 Interrupt 1
109 input iOTG_DREQ0, // ISP1362 DMA Request 0
110 input iOTG_DREQ1, // ISP1362 DMA Request 1
111 output oOTG_DACK0_N, // ISP1362 DMA Acknowledge 0
112 output oOTG_DACK1_N, // ISP1362 DMA Acknowledge 1
113 // // LCD Module 16X2 /// /
114 inout [ 7 : 0 ] LCD_D, // LCD Data bus 8 bits
115 output oLCD_ON, // LCD Power ON/OFF
116 output oLCD_BLON, // LCD Back Light ON/OFF
117 output oLCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
118 output oLCD_EN, // LCD Enable
119 output oLCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
120 // // SD Card Interface
121 inout SD_DAT, // SD Card Data
122 inout SD_DAT3, // SD Card Data 3
123 inout SD_CMD, // SD Card Command Signal
124 output oSD_CLK, // SD Card Clock
125 I2C // //
126 inout I2C_SDAT, // I2C Data
127 output oI2C_SCLK, // I2C Clock
128 PS2 // //
129 inout PS2_KBDAT, // PS2 Keyboard Data
130 inout PS2_KBCLK, // PS2 Keyboard Clock
131 inout PS2_MSDAT, // PS2 Mouse Data
132 inout PS2_MSCLK, // PS2 Mouse Clock
133 VGA /// /
134 output oVGA_CLOCK, // VGA Clock
135 output oVGA_HS, // VGA H_SYNC
136 output oVGA_VS, // VGA V_SYNC
137 output oVGA_BLANK_N, // VGA BLANK
138 output oVGA_SYNC_N, // VGA SYNC
139 output [ 9 : 0 ] oVGA_R, // VGA Red[9:0]
140 output [ 9 : 0 ] oVGA_G, // VGA Green[9:0]
141 output [ 9 : 0 ] oVGA_B, // VGA Blue[9:0]
142 /// / Ethernet Interface /// /
143 inout [ 15 : 0 ] ENET_D, // DM9000A DATA bus 16Bits
144 output oENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
145 output oENET_CS_N, // DM9000A Chip Select
146 output oENET_IOW_N, // DM9000A Write
147 output oENET_IOR_N, // DM9000A Read
148 output oENET_RESET_N, // DM9000A Reset
149 input iENET_INT, // DM9000A Interrupt
150 output oENET_CLK, // DM9000A Clock 25 MHz
151 // // Audio CODEC /// /
152 inout AUD_ADCLRCK, // Audio CODEC ADC LR Clock
153 input iAUD_ADCDAT, // Audio CODEC ADC Data
154 inout AUD_DACLRCK, // Audio CODEC DAC LR Clock
155 output oAUD_DACDAT, // Audio CODEC DAC Data
156 inout AUD_BCLK, // Audio CODEC Bit-Stream Clock
157 output oAUD_XCK, // Audio CODEC Chip Clock
158 // // TV Devoder /// /
159 input iTD1_CLK27, // TV Decoder1 Line_Lock Output Clock
160 input [ 7 : 0 ] iTD1_D, // TV Decoder1 Data bus 8 bits
161 input iTD1_HS, // TV Decoder1 H_SYNC
162 input iTD1_VS, // TV Decoder1 V_SYNC
163 output oTD1_RESET_N, // TV Decoder1 Reset
164 input iTD2_CLK27, // TV Decoder2 Line_Lock Output Clock
165 input [ 7 : 0 ] iTD2_D, // TV Decoder2 Data bus 8 bits
166 input iTD2_HS, // TV Decoder2 H_SYNC
167 input iTD2_VS, // TV Decoder2 V_SYNC
168 output oTD2_RESET_N, // TV Decoder2 Reset
169 GPIO // //
170 inout [ 31 : 0 ] GPIO_0, // GPIO Connection 0 I/O
171 input GPIO_CLKIN_N0, // GPIO Connection 0 Clock Input 0
172 input GPIO_CLKIN_P0, // GPIO Connection 0 Clock Input 1
173 inout GPIO_CLKOUT_N0, // GPIO Connection 0 Clock Output 0
174 inout GPIO_CLKOUT_P0, // GPIO Connection 0 Clock Output 1
175 inout [ 31 : 0 ] GPIO_1, // GPIO Connection 1 I/O
176 input GPIO_CLKIN_N1, // GPIO Connection 1 Clock Input 0
177 input GPIO_CLKIN_P1, // GPIO Connection 1 Clock Input 1
178 inout GPIO_CLKOUT_N1, // GPIO Connection 1 Clock Output 0
179 inout GPIO_CLKOUT_P1 // GPIO Connection 1 Clock Output 1
180 );
181
182 wire [ 11 : 0 ] CCD_DATA;
183 wire CCD_SDAT;
184 wire CCD_SCLK;
185 wire CCD_FLASH;
186 wire CCD_FVAL;
187 wire CCD_LVAL;
188 wire CCD_PIXCLK;
189 wire CCD_MCLK; // CCD Master Clock
190
191 wire [ 15 : 0 ] Read_DATA1;
192 wire [ 15 : 0 ] Read_DATA2;
193 wire VGA_CTRL_CLK;
194 wire [ 11 : 0 ] mCCD_DATA;
195 wire mCCD_DVAL;
196 wire mCCD_DVAL_d;
197 wire [ 15 : 0 ] X_Cont;
198 wire [ 15 : 0 ] Y_Cont;
199 wire [ 9 : 0 ] X_ADDR;
200 wire [ 31 : 0 ] Frame_Cont;
201 wire DLY_RST_0;
202 wire DLY_RST_1;
203 wire DLY_RST_2;
204 wire Read;
205 reg [ 11 : 0 ] rCCD_DATA;
206 reg rCCD_LVAL;
207 reg rCCD_FVAL;
208 wire [ 11 : 0 ] sCCD_R;
209 wire [ 11 : 0 ] sCCD_G;
210 wire [ 11 : 0 ] sCCD_B;
211 wire sCCD_DVAL;
212 reg [ 1 : 0 ] rClk;
213 wire sdram_ctrl_clk;
214
215 // Touch panel signal
216 wire [ 7 : 0 ] ltm_r; // LTM Red Data 8 Bits
217 wire [ 7 : 0 ] ltm_g; // LTM Green Data 8 Bits
218 wire [ 7 : 0 ] ltm_b; // LTM Blue Data 8 Bits
219 wire ltm_nclk; // LTM Clcok
220 wire ltm_hd;
221 wire ltm_vd;
222 wire ltm_den;
223 wire adc_dclk;
224 wire adc_cs;
225 wire adc_penirq_n;
226 wire adc_busy;
227 wire adc_din;
228 wire adc_dout;
229 wire adc_ltm_sclk;
230 wire ltm_grst;
231 // LTM Config
232 wire ltm_sclk;
233 wire ltm_sda;
234 wire ltm_scen;
235 wire ltm_3wirebusy_n;
236
237 assign CCD_DATA[ 0 ] = GPIO_1[ 11 ];
238 assign CCD_DATA[ 1 ] = GPIO_1[ 10 ];
239 assign CCD_DATA[ 2 ] = GPIO_1[ 9 ];
240 assign CCD_DATA[ 3 ] = GPIO_1[ 8 ];
241 assign CCD_DATA[ 4 ] = GPIO_1[ 7 ];
242 assign CCD_DATA[ 5 ] = GPIO_1[ 6 ];
243 assign CCD_DATA[ 6 ] = GPIO_1[ 5 ];
244 assign CCD_DATA[ 7 ] = GPIO_1[ 4 ];
245 assign CCD_DATA[ 8 ] = GPIO_1[ 3 ];
246 assign CCD_DATA[ 9 ] = GPIO_1[ 2 ];
247 assign CCD_DATA[ 10 ] = GPIO_1[ 1 ];
248 assign CCD_DATA[ 11 ] = GPIO_1[ 0 ];
249 assign GPIO_CLKOUT_N1 = CCD_MCLK;
250 assign CCD_FVAL = GPIO_1[ 18 ];
251 assign CCD_LVAL = GPIO_1[ 17 ];
252 assign CCD_PIXCLK = GPIO_CLKIN_N1;
253 assign GPIO_1[ 15 ] = 1 ' b1; // tRIGGER
254 assign GPIO_1[ 14 ] = DLY_RST_1;
255
256 assign oLEDR = iSW;
257 assign oLEDG = Y_Cont;
258
259 assign oTD1_RESET_N = 1 ' b1;
260 assign oVGA_CLOCK = VGA_CTRL_CLK;
261
262 assign CCD_MCLK = rClk[ 0 ];
263
264 assign oUART_TXD = iUART_RXD;
265
266 assign adc_penirq_n = GPIO_CLKIN_N0;
267 assign adc_dout = GPIO_0[ 0 ];
268 assign adc_busy = GPIO_CLKIN_P0;
269 assign GPIO_0[ 1 ] = adc_din;
270 assign GPIO_0[ 2 ] = adc_ltm_sclk;
271 assign GPIO_0[ 3 ] = ltm_b[ 3 ];
272 assign GPIO_0[ 4 ] = ltm_b[ 2 ];
273 assign GPIO_0[ 5 ] = ltm_b[ 1 ];
274 assign GPIO_0[ 6 ] = ltm_b[ 0 ];
275 assign GPIO_0[ 7 ] =~ ltm_nclk;
276 assign GPIO_0[ 8 ] = ltm_den;
277 assign GPIO_0[ 9 ] = ltm_hd;
278 assign GPIO_0[ 10 ] = ltm_vd;
279 assign GPIO_0[ 11 ] = ltm_b[ 4 ];
280 assign GPIO_0[ 12 ] = ltm_b[ 5 ];
281 assign GPIO_0[ 13 ] = ltm_b[ 6 ];
282 assign GPIO_CLKOUT_N0 = ltm_b[ 7 ];
283 assign GPIO_0[ 14 ] = ltm_g[ 0 ];
284 assign GPIO_CLKOUT_P0 = ltm_g[ 1 ];
285 assign GPIO_0[ 15 ] = ltm_g[ 2 ];
286 assign GPIO_0[ 16 ] = ltm_g[ 3 ];
287 assign GPIO_0[ 17 ] = ltm_g[ 4 ];
288 assign GPIO_0[ 18 ] = ltm_g[ 5 ];
289 assign GPIO_0[ 19 ] = ltm_g[ 6 ];
290 assign GPIO_0[ 20 ] = ltm_g[ 7 ];
291 assign GPIO_0[ 21 ] = ltm_r[ 0 ];
292 assign GPIO_0[ 22 ] = ltm_r[ 1 ];
293 assign GPIO_0[ 23 ] = ltm_r[ 2 ];
294 assign GPIO_0[ 24 ] = ltm_r[ 3 ];
295 assign GPIO_0[ 25 ] = ltm_r[ 4 ];
296 assign GPIO_0[ 26 ] = ltm_r[ 5 ];
297 assign GPIO_0[ 27 ] = ltm_r[ 6 ];
298 assign GPIO_0[ 28 ] = ltm_r[ 7 ];
299 assign GPIO_0[ 29 ] = ltm_grst;
300 assign GPIO_0[ 30 ] = ltm_scen;
301 assign GPIO_0[ 31 ] = ltm_sda;
302
303 assign ltm_grst = iKEY[ 0 ];
304 assign adc_ltm_sclk = ltm_sclk ;
305
306 always @( posedge iCLK_50)
307 rClk <= rClk + 1 ;
308
309 always @( posedge CCD_PIXCLK) begin
310 rCCD_DATA <= CCD_DATA;
311 rCCD_LVAL <= CCD_LVAL;
312 rCCD_FVAL <= CCD_FVAL;
313 end
314
315 Reset_Delay reset0 (
316 .iCLK(iCLK_50),
317 .iRST(iKEY[ 0 ]),
318 .oRST_0(DLY_RST_0),
319 .oRST_1(DLY_RST_1),
320 .oRST_2(DLY_RST_2)
321 );
322
323 CCD_Capture capture0 (
324 .oDATA(mCCD_DATA),
325 .oDVAL(mCCD_DVAL),
326 .oX_Cont(X_Cont),
327 .oY_Cont(Y_Cont),
328 .oFrame_Cont(Frame_Cont),
329 .iDATA(rCCD_DATA),
330 .iFVAL(rCCD_FVAL),
331 .iLVAL(rCCD_LVAL),
332 .iSTART( ! iKEY[ 3 ]),
333 .iEND( ! iKEY[ 2 ]),
334 .iCLK(CCD_PIXCLK),
335 .iRST(DLY_RST_2)
336 );
337
338 RAW2RGB raw0 (
339 .iCLK(CCD_PIXCLK),
340 .iRST_n(DLY_RST_1),
341 .iData(mCCD_DATA),
342 .iDval(mCCD_DVAL),
343 .oRed(sCCD_R),
344 .oGreen(sCCD_G),
345 .oBlue(sCCD_B),
346 .oDval(sCCD_DVAL),
347 .iMIRROR(iSW[ 17 ]),
348 .iX_Cont(X_Cont),
349 .iY_Cont(Y_Cont)
350 );
351
352 SEG7_LUT_8 seg0 (
353 .oSEG0(oHEX0_D),
354 .oSEG1(oHEX1_D),
355 .oSEG2(oHEX2_D),
356 .oSEG3(oHEX3_D),
357 .oSEG4(oHEX4_D),
358 .oSEG5(oHEX5_D),
359 .oSEG6(oHEX6_D),
360 .oSEG7(oHEX7_D),
361 .iDIG(Frame_Cont[ 31 : 0 ])
362 );
363
364 vga_pll vga_pll0 (
365 .inclk0(iCLK_50_2),
366 .c0(ltm_nclk)
367 );
368
369 sdram_pll sdram_pll0 (
370 .inclk0(iCLK_50_3),
371 .c0(sdram_ctrl_clk),
372 .c1(oDRAM0_CLK),
373 .c2(oDRAM1_CLK)
374 );
375
376 Sdram_Control_4Port sdram0 (
377 // HOST Side
378 .REF_CLK(iCLK_50),
379 .RESET_N( 1 ' b1),
380 .CLK(sdram_ctrl_clk),
381 // FIFO Write Side 1
382 .WR1_DATA({sCCD_G[ 11 : 7 ], sCCD_B[ 11 : 2 ]}),
383 .WR1(sCCD_DVAL),
384 .WR1_ADDR( 0 ),
385 .WR1_MAX_ADDR( 800 * 480 ),
386 .WR1_LENGTH( 9 ' h100),
387 .WR1_LOAD( ! DLY_RST_0),
388 .WR1_CLK(CCD_PIXCLK),
389 // FIFO Read Side 1
390 .RD1_DATA(Read_DATA1),
391 .RD1(wDVAL_binary),
392 .RD1_ADDR( 0 ),
393 .RD1_MAX_ADDR( 800 * 480 ),
394 .RD1_LENGTH( 9 ' h100),
395 .RD1_LOAD( ! DLY_RST_0),
396 .RD1_CLK( ~ ltm_nclk),
397 // SDRAM Side
398 .SA(oDRAM0_A[ 11 : 0 ]),
399 .BA(oDRAM0_BA),
400 .CS_N(oDRAM0_CS_N),
401 .CKE(oDRAM0_CKE),
402 .RAS_N(oDRAM0_RAS_N),
403 .CAS_N(oDRAM0_CAS_N),
404 .WE_N(oDRAM0_WE_N),
405 .DQ(DRAM_DQ[ 15 : 0 ]),
406 .DQM({oDRAM0_UDQM1,oDRAM0_LDQM0})
407 );
408
409 Sdram_Control_4Port sdram1 (
410 // HOST Side
411 .REF_CLK(iCLK_50),
412 .RESET_N( 1 ' b1),
413 .CLK(sdram_ctrl_clk),
414 // FIFO Write Side 1
415 .WR1_DATA({sCCD_G[ 6 : 2 ], sCCD_R[ 11 : 2 ]}),
416 .WR1(sCCD_DVAL),
417 .WR1_ADDR( 0 ),
418 .WR1_MAX_ADDR( 800 * 480 ),
419 .WR1_LENGTH( 9 ' h100),
420 .WR1_LOAD( ! DLY_RST_0),
421 .WR1_CLK(CCD_PIXCLK),
422 // FIFO Read Side 1
423 .RD1_DATA(Read_DATA2),
424 .RD1(wDVAL_binary),
425 .RD1_ADDR( 0 ),
426 .RD1_MAX_ADDR( 800 * 480 ),
427 .RD1_LENGTH( 9 ' h100),
428 .RD1_LOAD( ! DLY_RST_0),
429 .RD1_CLK( ~ ltm_nclk),
430 // SDRAM Side
431 .SA(oDRAM1_A[ 11 : 0 ]),
432 .BA(oDRAM1_BA),
433 .CS_N(oDRAM1_CS_N),
434 .CKE(oDRAM1_CKE),
435 .RAS_N(oDRAM1_RAS_N),
436 .CAS_N(oDRAM1_CAS_N),
437 .WE_N(oDRAM1_WE_N),
438 .DQ(DRAM_DQ[ 31 : 16 ]),
439 .DQM({oDRAM1_UDQM1,oDRAM1_LDQM0})
440 );
441
442 I2C_CCD_Config i2c_ccd_config0 (
443 // Host Side
444 .iCLK(iCLK_50),
445 .iRST_N(DLY_RST_1),
446 .iEXPOSURE_ADJ(iKEY[ 1 ]),
447 .iEXPOSURE_DEC_p(iSW[ 0 ]),
448 .iMIRROR_SW(iSW[ 17 ]),
449 // I2C Side
450 .I2C_SCLK(GPIO_1[ 20 ]),
451 .I2C_SDAT(GPIO_1[ 19 ])
452 );
453
454 touch_tcon vga0 (
455 .iCLK(ltm_nclk),
456 .iRST_n(DLY_RST_2),
457 // sdram side
458 .iREAD_DATA1({wDISP_G[ 9 : 5 ], wDISP_B}),
459 .iREAD_DATA2({wDISP_G[ 4 : 0 ], wDISP_R}),
460 .oREAD_SDRAM_EN(Read),
461 // lcd side
462 .oLCD_R(ltm_r),
463 .oLCD_G(ltm_g),
464 .oLCD_B(ltm_b),
465 .oHD(ltm_hd),
466 .oVD(ltm_vd),
467 .oDEN(ltm_den)
468 );
469
470 lcd_3wire_config lcd_config0 (
471 // Host Side
472 .iCLK(iCLK_50),
473 .iRST_n(DLY_RST_0),
474 // 3 wire Side
475 .o3WIRE_SCLK(ltm_sclk),
476 .io3WIRE_SDAT(ltm_sda),
477 .o3WIRE_SCEN(ltm_scen),
478 .o3WIRE_BUSY_n(ltm_3wirebusy_n)
479 );
480
481 // binary---------------------------------------------------
482 // RGB
483 wire [ 9 : 0 ] wVGA_R = Read_DATA2[ 9 : 0 ];
484 wire [ 9 : 0 ] wVGA_G = {Read_DATA1[ 14 : 10 ],Read_DATA2[ 14 : 10 ]};
485 wire [ 9 : 0 ] wVGA_B = Read_DATA1[ 9 : 0 ];
486
487 // binary
488 parameter THRESHOLD = 10 ' b0011111000;
489 wire wDVAL_binary;
490 wire [ 9 : 0 ] wBinary;
491
492 Binary binary0 (
493 .iCLK(ltm_nclk),
494 .iRST_N(DLY_RST_2),
495 .iTHRESHOLD(THRESHOLD),
496 .iDVAL(Read),
497 .iDATA(wVGA_G),
498 .oDVAL(wDVAL_binary),
499 .oDATA(wBinary)
500 );
501
502 // gray
503 wire [ 9 : 0 ] wGray_R = wVGA_G;
504 wire [ 9 : 0 ] wGray_G = wVGA_G;
505 wire [ 9 : 0 ] wGray_B = wVGA_G;
506
507 // to display
508 wire [ 9 : 0 ] wDISP_R = iSW[ 15 ] ? wGray_R : // Gray
509 iSW[ 14 ] ? wBinary : // Binary
510 wVGA_R; // Color
511 wire [ 9 : 0 ] wDISP_G = iSW[ 15 ] ? wGray_G : // Gray
512 iSW[ 14 ] ? wBinary : // Binary
513 wVGA_G; // Color
514 wire [ 9 : 0 ] wDISP_B = iSW[ 15 ] ? wGray_B : // Gray
515 iSW[ 14 ] ? wBinary : // Binary
516 wVGA_B; // Color
517
518 endmodule
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : DE2_70.v
5 Compiler : Quartus II 8.0
6 Description : Demo how to implement binary image on DE2-70
7 Release : 09/20/2008 1.0
8 */
9
10 module DE2_70 (
11 Clock Input
12 input iCLK_28, // 28.63636 MHz
13 input iCLK_50, // 50 MHz
14 input iCLK_50_2, // 50 MHz
15 input iCLK_50_3, // 50 MHz
16 input iCLK_50_4, // 50 MHz
17 input iEXT_CLOCK, // External Clock
18 Push Button
19 input [ 3 : 0 ] iKEY, // Pushbutton[3:0]
20 DPDT Switch
21 input [ 17 : 0 ] iSW, // Toggle Switch[17:0]
22 7-SEG Dispaly
23 output [ 6 : 0 ] oHEX0_D, // Seven Segment Digit 0
24 output oHEX0_DP, // Seven Segment Digit 0 decimal point
25 output [ 6 : 0 ] oHEX1_D, // Seven Segment Digit 1
26 output oHEX1_DP, // Seven Segment Digit 1 decimal point
27 output [ 6 : 0 ] oHEX2_D, // Seven Segment Digit 2
28 output oHEX2_DP, // Seven Segment Digit 2 decimal point
29 output [ 6 : 0 ] oHEX3_D, // Seven Segment Digit 3
30 output oHEX3_DP, // Seven Segment Digit 3 decimal point
31 output [ 6 : 0 ] oHEX4_D, // Seven Segment Digit 4
32 output oHEX4_DP, // Seven Segment Digit 4 decimal point
33 output [ 6 : 0 ] oHEX5_D, // Seven Segment Digit 5
34 output oHEX5_DP, // Seven Segment Digit 5 decimal point
35 output [ 6 : 0 ] oHEX6_D, // Seven Segment Digit 6
36 output oHEX6_DP, // Seven Segment Digit 6 decimal point
37 output [ 6 : 0 ] oHEX7_D, // Seven Segment Digit 7
38 output oHEX7_DP, // Seven Segment Digit 7 decimal point
39 /// / LED /// /
40 output [ 8 : 0 ] oLEDG, // LED Green[8:0]
41 output [ 17 : 0 ] oLEDR, // LED Red[17:0]
42 /// / UART /// /
43 output oUART_TXD, // UART Transmitter
44 input iUART_RXD, // UART Receiver
45 output oUART_CTS, // UART Clear To Send
46 input iUART_RTS, // UART Requst To Send
47 /// / IRDA /// /
48 output oIRDA_TXD, // IRDA Transmitter
49 input iIRDA_RXD, // IRDA Receiver
50 / // SDRAM Interface
51 inout [ 31 : 0 ] DRAM_DQ, // SDRAM Data bus 32 Bits
52 output [ 12 : 0 ] oDRAM0_A, // SDRAM0 Address bus 13 Bits
53 output [ 12 : 0 ] oDRAM1_A, // SDRAM1 Address bus 13 Bits
54 output oDRAM0_LDQM0, // SDRAM0 Low-byte Data Mask
55 output oDRAM1_LDQM0, // SDRAM1 Low-byte Data Mask
56 output oDRAM0_UDQM1, // SDRAM0 High-byte Data Mask
57 output oDRAM1_UDQM1, // SDRAM1 High-byte Data Mask
58 output oDRAM0_WE_N, // SDRAM0 Write Enable
59 output oDRAM1_WE_N, // SDRAM1 Write Enable
60 output oDRAM0_CAS_N, // SDRAM0 Column Address Strobe
61 output oDRAM1_CAS_N, // SDRAM1 Column Address Strobe
62 output oDRAM0_RAS_N, // SDRAM0 Row Address Strobe
63 output oDRAM1_RAS_N, // SDRAM1 Row Address Strobe
64 output oDRAM0_CS_N, // SDRAM0 Chip Select
65 output oDRAM1_CS_N, // SDRAM1 Chip Select
66 output [ 1 : 0 ] oDRAM0_BA, // SDRAM0 Bank Address
67 output [ 1 : 0 ] oDRAM1_BA, // SDRAM1 Bank Address
68 output oDRAM0_CLK, // SDRAM0 Clock
69 output oDRAM1_CLK, // SDRAM1 Clock
70 output oDRAM0_CKE, // SDRAM0 Clock Enable
71 output oDRAM1_CKE, // SDRAM1 Clock Enable
72 Flash Interface
73 inout [ 14 : 0 ] FLASH_DQ, // FLASH Data bus 15 Bits (0 to 14)
74 inout FLASH_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1
75 output [ 21 : 0 ] oFLASH_A, // FLASH Address bus 26 Bits
76 output oFLASH_WE_N, // FLASH Write Enable
77 output oFLASH_RST_N, // FLASH Reset
78 output oFLASH_WP_N, // FLASH Write Protect /Programming Acceleration
79 input iFLASH_RY_N, // FLASH Ready/Busy output
80 output oFLASH_BYTE_N, // FLASH Byte/Word Mode Configuration
81 output oFLASH_OE_N, // FLASH Output Enable
82 output oFLASH_CE_N, // FLASH Chip Enable
83 SRAM Interface
84 inout [ 31 : 0 ] SRAM_DQ, // SRAM Data Bus 32 Bits
85 inout [ 3 : 0 ] SRAM_DPA, // SRAM Parity Data Bus
86 output [ 18 : 0 ] oSRAM_A, // SRAM Address bus 21 Bits
87 output oSRAM_ADSC_N, // SRAM Controller Address Status
88 output oSRAM_ADSP_N, // SRAM Processor Address Status
89 output oSRAM_ADV_N, // SRAM Burst Address Advance
90 output [ 3 : 0 ] oSRAM_BE_N, // SRAM Byte Write Enable
91 output oSRAM_CE1_N, // SRAM Chip Enable
92 output oSRAM_CE2, // SRAM Chip Enable
93 output oSRAM_CE3_N, // SRAM Chip Enable
94 output oSRAM_CLK, // SRAM Clock
95 output oSRAM_GW_N, // SRAM Global Write Enable
96 output oSRAM_OE_N, // SRAM Output Enable
97 output oSRAM_WE_N, // SRAM Write Enable
98 // // ISP1362 Interface
99 inout [ 15 : 0 ] OTG_D, // ISP1362 Data bus 16 Bits
100 output [ 1 : 0 ] oOTG_A, // ISP1362 Address 2 Bits
101 output oOTG_CS_N, // ISP1362 Chip Select
102 output oOTG_OE_N, // ISP1362 Read
103 output oOTG_WE_N, // ISP1362 Write
104 output oOTG_RESET_N, // ISP1362 Reset
105 inout OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
106 inout OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
107 input iOTG_INT0, // ISP1362 Interrupt 0
108 input iOTG_INT1, // ISP1362 Interrupt 1
109 input iOTG_DREQ0, // ISP1362 DMA Request 0
110 input iOTG_DREQ1, // ISP1362 DMA Request 1
111 output oOTG_DACK0_N, // ISP1362 DMA Acknowledge 0
112 output oOTG_DACK1_N, // ISP1362 DMA Acknowledge 1
113 // // LCD Module 16X2 /// /
114 inout [ 7 : 0 ] LCD_D, // LCD Data bus 8 bits
115 output oLCD_ON, // LCD Power ON/OFF
116 output oLCD_BLON, // LCD Back Light ON/OFF
117 output oLCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
118 output oLCD_EN, // LCD Enable
119 output oLCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
120 // // SD Card Interface
121 inout SD_DAT, // SD Card Data
122 inout SD_DAT3, // SD Card Data 3
123 inout SD_CMD, // SD Card Command Signal
124 output oSD_CLK, // SD Card Clock
125 I2C // //
126 inout I2C_SDAT, // I2C Data
127 output oI2C_SCLK, // I2C Clock
128 PS2 // //
129 inout PS2_KBDAT, // PS2 Keyboard Data
130 inout PS2_KBCLK, // PS2 Keyboard Clock
131 inout PS2_MSDAT, // PS2 Mouse Data
132 inout PS2_MSCLK, // PS2 Mouse Clock
133 VGA /// /
134 output oVGA_CLOCK, // VGA Clock
135 output oVGA_HS, // VGA H_SYNC
136 output oVGA_VS, // VGA V_SYNC
137 output oVGA_BLANK_N, // VGA BLANK
138 output oVGA_SYNC_N, // VGA SYNC
139 output [ 9 : 0 ] oVGA_R, // VGA Red[9:0]
140 output [ 9 : 0 ] oVGA_G, // VGA Green[9:0]
141 output [ 9 : 0 ] oVGA_B, // VGA Blue[9:0]
142 /// / Ethernet Interface /// /
143 inout [ 15 : 0 ] ENET_D, // DM9000A DATA bus 16Bits
144 output oENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
145 output oENET_CS_N, // DM9000A Chip Select
146 output oENET_IOW_N, // DM9000A Write
147 output oENET_IOR_N, // DM9000A Read
148 output oENET_RESET_N, // DM9000A Reset
149 input iENET_INT, // DM9000A Interrupt
150 output oENET_CLK, // DM9000A Clock 25 MHz
151 // // Audio CODEC /// /
152 inout AUD_ADCLRCK, // Audio CODEC ADC LR Clock
153 input iAUD_ADCDAT, // Audio CODEC ADC Data
154 inout AUD_DACLRCK, // Audio CODEC DAC LR Clock
155 output oAUD_DACDAT, // Audio CODEC DAC Data
156 inout AUD_BCLK, // Audio CODEC Bit-Stream Clock
157 output oAUD_XCK, // Audio CODEC Chip Clock
158 // // TV Devoder /// /
159 input iTD1_CLK27, // TV Decoder1 Line_Lock Output Clock
160 input [ 7 : 0 ] iTD1_D, // TV Decoder1 Data bus 8 bits
161 input iTD1_HS, // TV Decoder1 H_SYNC
162 input iTD1_VS, // TV Decoder1 V_SYNC
163 output oTD1_RESET_N, // TV Decoder1 Reset
164 input iTD2_CLK27, // TV Decoder2 Line_Lock Output Clock
165 input [ 7 : 0 ] iTD2_D, // TV Decoder2 Data bus 8 bits
166 input iTD2_HS, // TV Decoder2 H_SYNC
167 input iTD2_VS, // TV Decoder2 V_SYNC
168 output oTD2_RESET_N, // TV Decoder2 Reset
169 GPIO // //
170 inout [ 31 : 0 ] GPIO_0, // GPIO Connection 0 I/O
171 input GPIO_CLKIN_N0, // GPIO Connection 0 Clock Input 0
172 input GPIO_CLKIN_P0, // GPIO Connection 0 Clock Input 1
173 inout GPIO_CLKOUT_N0, // GPIO Connection 0 Clock Output 0
174 inout GPIO_CLKOUT_P0, // GPIO Connection 0 Clock Output 1
175 inout [ 31 : 0 ] GPIO_1, // GPIO Connection 1 I/O
176 input GPIO_CLKIN_N1, // GPIO Connection 1 Clock Input 0
177 input GPIO_CLKIN_P1, // GPIO Connection 1 Clock Input 1
178 inout GPIO_CLKOUT_N1, // GPIO Connection 1 Clock Output 0
179 inout GPIO_CLKOUT_P1 // GPIO Connection 1 Clock Output 1
180 );
181
182 wire [ 11 : 0 ] CCD_DATA;
183 wire CCD_SDAT;
184 wire CCD_SCLK;
185 wire CCD_FLASH;
186 wire CCD_FVAL;
187 wire CCD_LVAL;
188 wire CCD_PIXCLK;
189 wire CCD_MCLK; // CCD Master Clock
190
191 wire [ 15 : 0 ] Read_DATA1;
192 wire [ 15 : 0 ] Read_DATA2;
193 wire VGA_CTRL_CLK;
194 wire [ 11 : 0 ] mCCD_DATA;
195 wire mCCD_DVAL;
196 wire mCCD_DVAL_d;
197 wire [ 15 : 0 ] X_Cont;
198 wire [ 15 : 0 ] Y_Cont;
199 wire [ 9 : 0 ] X_ADDR;
200 wire [ 31 : 0 ] Frame_Cont;
201 wire DLY_RST_0;
202 wire DLY_RST_1;
203 wire DLY_RST_2;
204 wire Read;
205 reg [ 11 : 0 ] rCCD_DATA;
206 reg rCCD_LVAL;
207 reg rCCD_FVAL;
208 wire [ 11 : 0 ] sCCD_R;
209 wire [ 11 : 0 ] sCCD_G;
210 wire [ 11 : 0 ] sCCD_B;
211 wire sCCD_DVAL;
212 reg [ 1 : 0 ] rClk;
213 wire sdram_ctrl_clk;
214
215 // Touch panel signal
216 wire [ 7 : 0 ] ltm_r; // LTM Red Data 8 Bits
217 wire [ 7 : 0 ] ltm_g; // LTM Green Data 8 Bits
218 wire [ 7 : 0 ] ltm_b; // LTM Blue Data 8 Bits
219 wire ltm_nclk; // LTM Clcok
220 wire ltm_hd;
221 wire ltm_vd;
222 wire ltm_den;
223 wire adc_dclk;
224 wire adc_cs;
225 wire adc_penirq_n;
226 wire adc_busy;
227 wire adc_din;
228 wire adc_dout;
229 wire adc_ltm_sclk;
230 wire ltm_grst;
231 // LTM Config
232 wire ltm_sclk;
233 wire ltm_sda;
234 wire ltm_scen;
235 wire ltm_3wirebusy_n;
236
237 assign CCD_DATA[ 0 ] = GPIO_1[ 11 ];
238 assign CCD_DATA[ 1 ] = GPIO_1[ 10 ];
239 assign CCD_DATA[ 2 ] = GPIO_1[ 9 ];
240 assign CCD_DATA[ 3 ] = GPIO_1[ 8 ];
241 assign CCD_DATA[ 4 ] = GPIO_1[ 7 ];
242 assign CCD_DATA[ 5 ] = GPIO_1[ 6 ];
243 assign CCD_DATA[ 6 ] = GPIO_1[ 5 ];
244 assign CCD_DATA[ 7 ] = GPIO_1[ 4 ];
245 assign CCD_DATA[ 8 ] = GPIO_1[ 3 ];
246 assign CCD_DATA[ 9 ] = GPIO_1[ 2 ];
247 assign CCD_DATA[ 10 ] = GPIO_1[ 1 ];
248 assign CCD_DATA[ 11 ] = GPIO_1[ 0 ];
249 assign GPIO_CLKOUT_N1 = CCD_MCLK;
250 assign CCD_FVAL = GPIO_1[ 18 ];
251 assign CCD_LVAL = GPIO_1[ 17 ];
252 assign CCD_PIXCLK = GPIO_CLKIN_N1;
253 assign GPIO_1[ 15 ] = 1 ' b1; // tRIGGER
254 assign GPIO_1[ 14 ] = DLY_RST_1;
255
256 assign oLEDR = iSW;
257 assign oLEDG = Y_Cont;
258
259 assign oTD1_RESET_N = 1 ' b1;
260 assign oVGA_CLOCK = VGA_CTRL_CLK;
261
262 assign CCD_MCLK = rClk[ 0 ];
263
264 assign oUART_TXD = iUART_RXD;
265
266 assign adc_penirq_n = GPIO_CLKIN_N0;
267 assign adc_dout = GPIO_0[ 0 ];
268 assign adc_busy = GPIO_CLKIN_P0;
269 assign GPIO_0[ 1 ] = adc_din;
270 assign GPIO_0[ 2 ] = adc_ltm_sclk;
271 assign GPIO_0[ 3 ] = ltm_b[ 3 ];
272 assign GPIO_0[ 4 ] = ltm_b[ 2 ];
273 assign GPIO_0[ 5 ] = ltm_b[ 1 ];
274 assign GPIO_0[ 6 ] = ltm_b[ 0 ];
275 assign GPIO_0[ 7 ] =~ ltm_nclk;
276 assign GPIO_0[ 8 ] = ltm_den;
277 assign GPIO_0[ 9 ] = ltm_hd;
278 assign GPIO_0[ 10 ] = ltm_vd;
279 assign GPIO_0[ 11 ] = ltm_b[ 4 ];
280 assign GPIO_0[ 12 ] = ltm_b[ 5 ];
281 assign GPIO_0[ 13 ] = ltm_b[ 6 ];
282 assign GPIO_CLKOUT_N0 = ltm_b[ 7 ];
283 assign GPIO_0[ 14 ] = ltm_g[ 0 ];
284 assign GPIO_CLKOUT_P0 = ltm_g[ 1 ];
285 assign GPIO_0[ 15 ] = ltm_g[ 2 ];
286 assign GPIO_0[ 16 ] = ltm_g[ 3 ];
287 assign GPIO_0[ 17 ] = ltm_g[ 4 ];
288 assign GPIO_0[ 18 ] = ltm_g[ 5 ];
289 assign GPIO_0[ 19 ] = ltm_g[ 6 ];
290 assign GPIO_0[ 20 ] = ltm_g[ 7 ];
291 assign GPIO_0[ 21 ] = ltm_r[ 0 ];
292 assign GPIO_0[ 22 ] = ltm_r[ 1 ];
293 assign GPIO_0[ 23 ] = ltm_r[ 2 ];
294 assign GPIO_0[ 24 ] = ltm_r[ 3 ];
295 assign GPIO_0[ 25 ] = ltm_r[ 4 ];
296 assign GPIO_0[ 26 ] = ltm_r[ 5 ];
297 assign GPIO_0[ 27 ] = ltm_r[ 6 ];
298 assign GPIO_0[ 28 ] = ltm_r[ 7 ];
299 assign GPIO_0[ 29 ] = ltm_grst;
300 assign GPIO_0[ 30 ] = ltm_scen;
301 assign GPIO_0[ 31 ] = ltm_sda;
302
303 assign ltm_grst = iKEY[ 0 ];
304 assign adc_ltm_sclk = ltm_sclk ;
305
306 always @( posedge iCLK_50)
307 rClk <= rClk + 1 ;
308
309 always @( posedge CCD_PIXCLK) begin
310 rCCD_DATA <= CCD_DATA;
311 rCCD_LVAL <= CCD_LVAL;
312 rCCD_FVAL <= CCD_FVAL;
313 end
314
315 Reset_Delay reset0 (
316 .iCLK(iCLK_50),
317 .iRST(iKEY[ 0 ]),
318 .oRST_0(DLY_RST_0),
319 .oRST_1(DLY_RST_1),
320 .oRST_2(DLY_RST_2)
321 );
322
323 CCD_Capture capture0 (
324 .oDATA(mCCD_DATA),
325 .oDVAL(mCCD_DVAL),
326 .oX_Cont(X_Cont),
327 .oY_Cont(Y_Cont),
328 .oFrame_Cont(Frame_Cont),
329 .iDATA(rCCD_DATA),
330 .iFVAL(rCCD_FVAL),
331 .iLVAL(rCCD_LVAL),
332 .iSTART( ! iKEY[ 3 ]),
333 .iEND( ! iKEY[ 2 ]),
334 .iCLK(CCD_PIXCLK),
335 .iRST(DLY_RST_2)
336 );
337
338 RAW2RGB raw0 (
339 .iCLK(CCD_PIXCLK),
340 .iRST_n(DLY_RST_1),
341 .iData(mCCD_DATA),
342 .iDval(mCCD_DVAL),
343 .oRed(sCCD_R),
344 .oGreen(sCCD_G),
345 .oBlue(sCCD_B),
346 .oDval(sCCD_DVAL),
347 .iMIRROR(iSW[ 17 ]),
348 .iX_Cont(X_Cont),
349 .iY_Cont(Y_Cont)
350 );
351
352 SEG7_LUT_8 seg0 (
353 .oSEG0(oHEX0_D),
354 .oSEG1(oHEX1_D),
355 .oSEG2(oHEX2_D),
356 .oSEG3(oHEX3_D),
357 .oSEG4(oHEX4_D),
358 .oSEG5(oHEX5_D),
359 .oSEG6(oHEX6_D),
360 .oSEG7(oHEX7_D),
361 .iDIG(Frame_Cont[ 31 : 0 ])
362 );
363
364 vga_pll vga_pll0 (
365 .inclk0(iCLK_50_2),
366 .c0(ltm_nclk)
367 );
368
369 sdram_pll sdram_pll0 (
370 .inclk0(iCLK_50_3),
371 .c0(sdram_ctrl_clk),
372 .c1(oDRAM0_CLK),
373 .c2(oDRAM1_CLK)
374 );
375
376 Sdram_Control_4Port sdram0 (
377 // HOST Side
378 .REF_CLK(iCLK_50),
379 .RESET_N( 1 ' b1),
380 .CLK(sdram_ctrl_clk),
381 // FIFO Write Side 1
382 .WR1_DATA({sCCD_G[ 11 : 7 ], sCCD_B[ 11 : 2 ]}),
383 .WR1(sCCD_DVAL),
384 .WR1_ADDR( 0 ),
385 .WR1_MAX_ADDR( 800 * 480 ),
386 .WR1_LENGTH( 9 ' h100),
387 .WR1_LOAD( ! DLY_RST_0),
388 .WR1_CLK(CCD_PIXCLK),
389 // FIFO Read Side 1
390 .RD1_DATA(Read_DATA1),
391 .RD1(wDVAL_binary),
392 .RD1_ADDR( 0 ),
393 .RD1_MAX_ADDR( 800 * 480 ),
394 .RD1_LENGTH( 9 ' h100),
395 .RD1_LOAD( ! DLY_RST_0),
396 .RD1_CLK( ~ ltm_nclk),
397 // SDRAM Side
398 .SA(oDRAM0_A[ 11 : 0 ]),
399 .BA(oDRAM0_BA),
400 .CS_N(oDRAM0_CS_N),
401 .CKE(oDRAM0_CKE),
402 .RAS_N(oDRAM0_RAS_N),
403 .CAS_N(oDRAM0_CAS_N),
404 .WE_N(oDRAM0_WE_N),
405 .DQ(DRAM_DQ[ 15 : 0 ]),
406 .DQM({oDRAM0_UDQM1,oDRAM0_LDQM0})
407 );
408
409 Sdram_Control_4Port sdram1 (
410 // HOST Side
411 .REF_CLK(iCLK_50),
412 .RESET_N( 1 ' b1),
413 .CLK(sdram_ctrl_clk),
414 // FIFO Write Side 1
415 .WR1_DATA({sCCD_G[ 6 : 2 ], sCCD_R[ 11 : 2 ]}),
416 .WR1(sCCD_DVAL),
417 .WR1_ADDR( 0 ),
418 .WR1_MAX_ADDR( 800 * 480 ),
419 .WR1_LENGTH( 9 ' h100),
420 .WR1_LOAD( ! DLY_RST_0),
421 .WR1_CLK(CCD_PIXCLK),
422 // FIFO Read Side 1
423 .RD1_DATA(Read_DATA2),
424 .RD1(wDVAL_binary),
425 .RD1_ADDR( 0 ),
426 .RD1_MAX_ADDR( 800 * 480 ),
427 .RD1_LENGTH( 9 ' h100),
428 .RD1_LOAD( ! DLY_RST_0),
429 .RD1_CLK( ~ ltm_nclk),
430 // SDRAM Side
431 .SA(oDRAM1_A[ 11 : 0 ]),
432 .BA(oDRAM1_BA),
433 .CS_N(oDRAM1_CS_N),
434 .CKE(oDRAM1_CKE),
435 .RAS_N(oDRAM1_RAS_N),
436 .CAS_N(oDRAM1_CAS_N),
437 .WE_N(oDRAM1_WE_N),
438 .DQ(DRAM_DQ[ 31 : 16 ]),
439 .DQM({oDRAM1_UDQM1,oDRAM1_LDQM0})
440 );
441
442 I2C_CCD_Config i2c_ccd_config0 (
443 // Host Side
444 .iCLK(iCLK_50),
445 .iRST_N(DLY_RST_1),
446 .iEXPOSURE_ADJ(iKEY[ 1 ]),
447 .iEXPOSURE_DEC_p(iSW[ 0 ]),
448 .iMIRROR_SW(iSW[ 17 ]),
449 // I2C Side
450 .I2C_SCLK(GPIO_1[ 20 ]),
451 .I2C_SDAT(GPIO_1[ 19 ])
452 );
453
454 touch_tcon vga0 (
455 .iCLK(ltm_nclk),
456 .iRST_n(DLY_RST_2),
457 // sdram side
458 .iREAD_DATA1({wDISP_G[ 9 : 5 ], wDISP_B}),
459 .iREAD_DATA2({wDISP_G[ 4 : 0 ], wDISP_R}),
460 .oREAD_SDRAM_EN(Read),
461 // lcd side
462 .oLCD_R(ltm_r),
463 .oLCD_G(ltm_g),
464 .oLCD_B(ltm_b),
465 .oHD(ltm_hd),
466 .oVD(ltm_vd),
467 .oDEN(ltm_den)
468 );
469
470 lcd_3wire_config lcd_config0 (
471 // Host Side
472 .iCLK(iCLK_50),
473 .iRST_n(DLY_RST_0),
474 // 3 wire Side
475 .o3WIRE_SCLK(ltm_sclk),
476 .io3WIRE_SDAT(ltm_sda),
477 .o3WIRE_SCEN(ltm_scen),
478 .o3WIRE_BUSY_n(ltm_3wirebusy_n)
479 );
480
481 // binary---------------------------------------------------
482 // RGB
483 wire [ 9 : 0 ] wVGA_R = Read_DATA2[ 9 : 0 ];
484 wire [ 9 : 0 ] wVGA_G = {Read_DATA1[ 14 : 10 ],Read_DATA2[ 14 : 10 ]};
485 wire [ 9 : 0 ] wVGA_B = Read_DATA1[ 9 : 0 ];
486
487 // binary
488 parameter THRESHOLD = 10 ' b0011111000;
489 wire wDVAL_binary;
490 wire [ 9 : 0 ] wBinary;
491
492 Binary binary0 (
493 .iCLK(ltm_nclk),
494 .iRST_N(DLY_RST_2),
495 .iTHRESHOLD(THRESHOLD),
496 .iDVAL(Read),
497 .iDATA(wVGA_G),
498 .oDVAL(wDVAL_binary),
499 .oDATA(wBinary)
500 );
501
502 // gray
503 wire [ 9 : 0 ] wGray_R = wVGA_G;
504 wire [ 9 : 0 ] wGray_G = wVGA_G;
505 wire [ 9 : 0 ] wGray_B = wVGA_G;
506
507 // to display
508 wire [ 9 : 0 ] wDISP_R = iSW[ 15 ] ? wGray_R : // Gray
509 iSW[ 14 ] ? wBinary : // Binary
510 wVGA_R; // Color
511 wire [ 9 : 0 ] wDISP_G = iSW[ 15 ] ? wGray_G : // Gray
512 iSW[ 14 ] ? wBinary : // Binary
513 wVGA_G; // Color
514 wire [ 9 : 0 ] wDISP_B = iSW[ 15 ] ? wGray_B : // Gray
515 iSW[ 14 ] ? wBinary : // Binary
516 wVGA_B; // Color
517
518 endmodule
481行以下為從DE2_70_D5M_LTM範例所加增加的code
488行
parameter
THRESHOLD
=
10
'
b0011111000;
設定threshold常數，可依需求自行設定。
483行
//
RGB
assign wVGA_R = Read_DATA2[ 9 : 0 ];
assign wVGA_G = {Read_DATA1[ 14 : 10 ],Read_DATA2[ 14 : 10 ]};
assign wVGA_B = Read_DATA1[ 9 : 0 ];
assign wVGA_R = Read_DATA2[ 9 : 0 ];
assign wVGA_G = {Read_DATA1[ 14 : 10 ],Read_DATA2[ 14 : 10 ]};
assign wVGA_B = Read_DATA1[ 9 : 0 ];
從SDRAM接出的wire，準備連進Binary module。
492行
Binary binary0 (
.iCLK(ltm_nclk),
.iRST_N(DLY_RST_2),
.iTHRESHOLD(THRESHOLD),
.iDVAL(Read),
.iDATA(wVGA_G),
.oDVAL(wDVAL_b),
.oDATA(wBinary)
);
.iCLK(ltm_nclk),
.iRST_N(DLY_RST_2),
.iTHRESHOLD(THRESHOLD),
.iDVAL(Read),
.iDATA(wVGA_G),
.oDVAL(wDVAL_b),
.oDATA(wBinary)
);
使用與LTM Controller相同的clock與reset，如系統架構圖所示，資料從SDRAM Controller經過Binary module後，再傳入LTM Controller。
508行
//
To Display
assign wDISP_R = iSW[ 15 ] ? wGray_R : // Gray
iSW[ 14 ] ? wBinary : // Binary
wVGA_R; // Color
assign wDISP_G = iSW[ 15 ] ? wGray_G : // Gray
iSW[ 14 ] ? wBinary : // Binary
wVGA_G; // Color
assign wDISP_B = iSW[ 15 ] ? wGray_B : // Gray
iSW[ 14 ] ? wBinary : // Binary
wVGA_B; // Color
assign wDISP_R = iSW[ 15 ] ? wGray_R : // Gray
iSW[ 14 ] ? wBinary : // Binary
wVGA_R; // Color
assign wDISP_G = iSW[ 15 ] ? wGray_G : // Gray
iSW[ 14 ] ? wBinary : // Binary
wVGA_G; // Color
assign wDISP_B = iSW[ 15 ] ? wGray_B : // Gray
iSW[ 14 ] ? wBinary : // Binary
wVGA_B; // Color
加上了SW控制，可切換顯示彩色、灰階與binary image。
操作方式
KEY[0]：reset
KEY[1]：調整曝光值
KEY[2]：capture
KEY[3]：free run
SW[0]：on：減少曝光值模式，off : 增加曝光值模式
SW[15]：on：灰階模式，off：彩色模式
SW[15] off + SW[14] on：Binary Image模式
SW[17]：on：啟動mirror，off：不啟動mirror
執行結果
依次為：彩色模式、灰階模式、Binary Image模式
完整程式下載
DE2_70_D5M_LTM_binary.7z
Conclusion
利用binary image的基礎，接著將討論如何用Verilog實現一些影像前處理的演算法，如Dilation、Erosion、Openning、Closing、Median Filter...等。
See Also
(原創) 如何将图片转成Binary Image? (.NET) (ASP.NET) (C#) (GDI+) (Image Processing)
(原創) 如何實現Real Time對Binary Image做Dilation? (SOC) (Verilog) (Image Processing) (DE2-70) (TRDB-D5M) (TRDB-LTM)
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