Voltage Translation for Analog to Digital Interface ADC
http://openschemes.com/2010/03/23/zeroplus-logic-cube-review-and-teardown/
LAP 16032 has 4.5MBIT SRAM and can aquire up to 128k per chn, now my LAP 16032 has 18MBIT SRAM
The device scores high marks on our chart for:
- Dependability - You plug it in, and it does what it says it’s going to. No screwing around with dodgy drivers and flaky hardware. These guys really do seem to use their own hardware, and it shows. FEBE? For engineers, by engineers?
- Reliability - It always does what it says it’s going to do. It doesn’t miss edges or do other stupid stuff. Ever, as far as we can tell and that’s a big plus for us.
- Portability - It’s nice that the whole setup: Cube, USB cable, fancy colored wires, and some minigrabbers all fit nicely in a ziplock bag. Keeps it fresh, as well.
- Capability - Depending on how much money you’re willing to spend, you can get a device with 16 or 32 channels, and memory ranging from 32k to 2MB. That’s a lotta sampling! But since these guys aren’t stupid, they added some pretty awesome triggering and compression that gives you tons of sampling with very little memory. Also, the plug-in protocol analyzers are fantastic. We hate counting I2C clocks and writing hex characters by hand, so having the software do all the work is great.
- Hackability - Due to economies of scale naturally found in manufacturing, the board we got (smallest mem, lowest channels) was able to be upgraded to a pretty awesome box for just about $10. Oh, that and a shitload of work. But that stuff’s considered fun over here.
Teardown & Functional Description
Teardown is dead freakin easy. Remove the 4 rubber feet on the bottom/back to reveal 4 totally goofy sheet-metal looking screws. The only part of the device that was oddly low-quality was these screws. Not a big deal, but when you open and close the box about a thousand times, you think how ugly they are about a thousand times. Guess it stuck.
LAP-C is what they call it, so that’s what we’ll be calling it too. Guess it’s the lower-end of what ZeroPlus manufactures, but it’s fine for us. Blows SUMP clean out of the water, and trust us – we love SUMP! But you get what you pay for, really.
One thing you’ll notice is that we’re blurring out the device’s serial number. Why? Well when we went googling, we found that all the serial numbers were always blurred out. It occurred to us that the image of a serial number must be considered pornographic in Taiwan, so we decided to blur ours in order to show respect.
Sure, the protocol licensing is tied to the serial number among other things, but unless we showed our serial number AND our license key, AND you changed your device’s serial number to ours – we can see no way that the public viewing of a serial number could in any way affect ZP. But still blurred – and hence, they must either be highly offensive or highly arousing and in either case are not suitable for public viewing.
Once you’ve gotten the case off, you can see the LAP-C is a single-board device centered around a big old custom ASIC. We’re not sure if it’s truly custom but since there’s no platform flash nearby it’s not a repackaged Xilinx. Anyway, we trust ZP to be able to make an ASIC and have no need to decap this one, so this chip stays unmolested.
As we said before, we bought the cheapest one (LAPC 16032, 16 channel, 32k RAM) in hopes that we could hack it up. Keep that in mind when reviewing the pix.
We’ll give a quick rundown of the operation. USB comes in on a Genesys Logic GL-660 old-school USB->IEEE1284 controller, which must have been a legacy design as the 660 is all but dead as far as we can tell. Here’s a GL-660USB Datasheet that really gives very little information. We’re trying to determine if the 660 can write his own serial eeprom over USB, so if you know either way – plz contact us!
The GL660 interfaces directly to the ASIC, so let’s go there next. It’s a ZeroPlus custom as we said before, marked ZP322MB-5. Let’s inspect that again. ZP 32 2MB -5. Uh, looks like our chip is actually a 32 channel, 2MB RAM device. Well that’s the top of the line analyzer there, buddy. How’d we get that top-of-the-line chip in our crappy little 16032?
Economies of scale! It’s way cheaper to make two of the same chip than one each of two types, so the standard practice is to make one full-featured IC and disable features for the peons who can’t afford those features. It’s great for the manufacturer, and the loss due to nerds like us hacking in those missing features is still less than the cost of running two sets of wafers. Now is that a bad thing to do? Are we subverting something we shouldn’t? What are the ethics of “hacking in” features.
We think of it like this: If you buy a Honda Civic, nobody would think twice about you ripping open the engine and installing a turbo or something. Now you’ve added $5k to the value of the car for the few hundred bucks the turbo hardware would cost. It’s the same thing here – we’re like mechanics for electronics. We have the expertise, and enjoy the challenge so we will add, subtract, cut, patch, solder, and reflash whatever we can in order to soup up our toys..
So we know the main IC probably has the capability to do more than what the label says. Let’s keep going. The RAM chip just north of the ASIC is a Cypress CY7C1347G, which is a 4Mbit (128k x 36) pipelined synchronous ram (that means fast, and does stuff on clock edge only in order to be fast). We make the guess that the width of 36 is probably used for 32 channels, so our installed RAM is 128k, not 32k!
That’s kind of weird – economies of scale don’t really apply to things like RAM because the “feature” is directly proportional to die size. Cutting the ram in half requires just over half the silicon (fixed overhead for address decoder and sense amps, but half the cells) so the cost is nearly linear. Cypress must have a SIGNIFICANT volume discount for buying multiple chips of one type instead of fewer chips of multiple types. In other words – Cypress is gouging the small
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