PCI & PCIE Configuration Register Space

1、PCI-Compatible Configuration
bits [1:0] are hard-wired, read-only and must return zeros when read.
bits [7:2] identify the target dword
bits [10:8] identify the target function number (1-of-8) within the target device.
bits [15:11] identify the target device number (1-of-32).
bits [23:16] identifies the target bus number (1-of-256).
bits [30:24] are reserved and must be zero.
bit 31 must be set to a one, enabling the translation of a subsequent processor IO access to the Configuration Data Port into a configuration access. If bit 31 is zero and the processor initiates an IO read from or IO write to the Configuration Data Port, the transaction is treated as an IO transaction request.

 

2、PCI Express Enhanced Configuration
Address bits 63:28 indicates the 256MB-aligned base address of the overall Enhanced Configuration address range.
Address bits 27:20 select the target bus (1-of-256).
Address bits 19:15 select the target device (1-of-32) on the bus.
Address bits 14:12 select the target function (1-of-8) within the device.
Address bits 11:2 selects the target dword (1-of-1024) within the selected function's configuration space.
Address bits 1:0 define the start byte location within the selected dword.

 

3、PCIE Configuration Register Space访问方式

memory-mapped physical address = PCI Express* Config Space Base Address Bus Number * 100000h Device Number * 8000h Function Number * 1000h Register Offset.
其中PCI Express* Config Space Base Address 保存在某一PCI Device Register中，查看對應CPU EDS 中的 MMCFG_Rule，獲得此PCI Device 并從相應offset讀取PCI Express* Config Space Base Address.
PS：其中0--FF部份既可用上述方法訪問，也可通過I/O Map(cf8、cfc端口) 訪問。

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