计算机组成与结构习题答案,计算机组成与结构习题答案

计算机组成与结构习题答案

第三章 1．某微处理器指令集包含如下指令。将每条指令按数据传送，数据运算或者程 序控制进行分类。 a) XTOY(X＝Y) b) CLX(X＝0) c) JX Г(IF X＝1 THEN GOTO Г) d) XMLY(X＝X×Y) e) XNEG(X＝X’＋1) 解：a) Data movement b) Data operation c) Program control d) Data operation e) Data operation 6. 对于8085微处理器，下面每条指令采用了何种寻址方式？ a) MOV r1,r2 b) LXI rp，Г c) SPHL d) ACI n e) JUMP Г 解：a) Register Direct b) Immediate c) Implicit d) Immediate e) Immediate 9. 已知R＝10，PC＝20，变址寄存器X＝30，写出下列指令的累加器的值。所 有的内存单元Q包括了值Q＋1。每条指令占用两个内存单元。 a) LDAC 10 b) LDAC(10) c) LDAC R d) LDAC @R e) LDAC ＃10 f) LDAC $10 g) LDAC 10(X) 解：a) AC = 11 b) AC = 12 c) AC = 10 d) AC = 11 e) AC = 10 f) AC = 33 g) AC = 41 19. LDAC 1001H MVAC LDAC 1002H ADD MVAC LDAC 1003H ADD MVAC LDAC 1004H ADD MVAC LDAC 1005H LDAC 1006H ADD MVAC LDAC 1007H ADD MVAC LDAC 1008H ADD MVAC LDAC 1009H ADD MVACADD MVAC LDAC 100AH ADD STAC 1000H 20. Loop: LXI H, 1001H MVI B,0AH XRA A ADD M INX H DCR B JNZ Loop STA 1000H 第四章 6. 8、用 16×2的存储器芯片、为一个有 8位地址总线的计算机设计一个 32×8的存储器子系 统，该子系统带低位交叉的地址。13、若某计算机系统采用单独 I/O，试为地址为二进制 1010 1010的输入设备设计一个接口。 解： 17、若某计算机系统采用单独 I/O，试为地址为二进制 1000 0001的双向输入/输出设备设 计一个接口。 解：20、解：Chapter 5 3.解：a) : X  Y: X  Y b) : X  0: X  X 4、 (a) (b) 8. a) 0011 0010 0000 0100 b) 0100 1100 1000 0001 c) 0011 0010 0000 0101 d) 0100 1100 1000 0001 e) 1011 0010 0000 0100 f) 1100 1100 1000 0001 g) 1001 0000 0010 0000 h) 0000 1001 1001 0000 Chapter 6 2． 解： 2. Instruction Instruction CodeOperation ADDADD 00AAAAAA AC  AC + M[AAAAAA] + M[AAAAAA + 1] ANDSKIP 01AAAAAA AC  AC ^ M[AAAAAA], PC  PC + 1 INCAND 1XAAAAAA AC  (AC + 1) ^ M[AAAAAA] 4. 解：5. 解：Change the to the counter to X, X , Y, X  Y.Change INC IA3 to IA2.Change CLR IA2 to IA3. 10.解： (IR must have 4 bits instead of 2.) FETCH3:IR  DR[74], AR  DR[50] MVAC1: R  AC MOVR1: AC  R 11. i.) IR must have 4 bits instead of 2. It receives bus bits 74 as its s. During FETCH3, bit DR[54] is sent to both IR and AR. This is shown below. ii) Register R is added to the CPU. It receives data from the bus and sends data to the bus through tri-state buffers. It requires only a LD signal. This is shown below. iii) The ALU is modified as shown below. 12. Arbitrarily assign MVAC1 and MOVR1 to decoder outputs 6 and 7, respectively. i) New to counter: (IR 3^ IR 2^ IR 1 ) , IR[32],(IR 3^ IR 2^ IR 1^ IR 0 .). ii) Add MVAC1 and MOVR1 to the s of the OR gate driving counter CLR. iii) New control signals RLOAD = MVAC1 and RBUS = MOVR1. iv) Add MOVR1 to the s of the OR gate generating ACLOAD.13. Test program: 0: MVAC 1: MOVR Instruction State Operations pered Next state MVAC FETCH1 AR  0 FETCH2 FETCH2 DR  E0H, PC  1 FETCH3 FETCH3 IR  1110, AR  20H MVAC1 MVAC1 R  1 FETCH1 MOVR FETCH1 AR  1 FETCH2 FETCH2 DR  F0H, PC  2 FETCH3 FETCH3 IR  1111, AR  30H MOVR1 MOVR1 AC 1 FETCH1 29. State diagram and RTL code: FETCH1:AR  PC ADD1: DR  M, PC  PC + 1 FETCH2:DR  M, PC  PC + 1 ADD2: AC  AC + DR FETCH3:IR  DR[75], AR  PC OR1: DR  M, PC  PC + 1 LDI1: DR  M, PC  PC + 1 OR2: AC 