am335x linux 定时器,为AM335x移植Linux内核主线代码(28)有关时钟

About clock!

There is no need to modify clock settings of default u-boot until debugging LCD.

So, let's begin.

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AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual

Chapter 8 Power, Reset, and Clock Management (PRCM)

8.1 Power, Reset, and Clock Management

8.1.1 Introduction

The device power-management architecture ensures maximum performance and operation time for user satisfaction (audio/video support) while offering versatile power-management techniques for maximum design flexibility, depending on application requirements. This introduction contains the following information:

* Power-management architecture building blocks for the device

* State-of-the-art power management techniques supported by the power-management architecture of the device

8.1.2 Device Power-Management Architecture Building Blocks

To provide a versatile architecture supporting multiple power-management techniques, the power-management framework is built with three levels of resource management: clock, power, and voltage management.

These management levels are enforced by defining the managed entities or building blocks of the power-management architecture, called the clock, power, and voltage domains. A domain is a group of modules or subsections of the device that share a common entity (for example, common clock source, common voltage source, or common power switch). The group forming the domain is managed by a policy manager. For example, a clock for a clock domain is managed by a dedicated clock manager within power, reset, and clock management (PRCM) module. The clock manager considers the joint clocking constraints of all the modules belonging to that clock domain (and, hence, receiving the clock).

8.1.3 Clock Management

The PRCM module along with the control module manages the gating (that is, switching off) and enabling of the clocks to the device modules.

(Note: Control module is belonging to chapter 9.)

8.1.3.1 Module Interface and Functional Clocks

Each module within the device has specific clock input characteristic requirements. Based on the characteristics of the clocks delivered to the modules, the clocks are divided into two categories: interface clocks and functional clocks.

The interface clocks have the following characteristics:

* They ensure proper communication between any module/subsystem and interconnect.

* In most cases, they supply the system interconnect interface and registers of the module.

* A typical module has one interface clock, but modules with multiple interface clocks may also exist (that is, when connected to multiple interconnect buses).

* Interface clock management is done at the device level.

* From the standpoint of the PRCM module, an interface clock is identified by an _ICLK suffix.

Functional clocks have the following characteristics:

* The supply the functional part of a module or subsystem.

* A module can have one or more functional clocks. Some functional clocks are mandatory, while others are optional. A module needs its mandatory clock(s) to be operational. The optional clocks are used for specific features and can be shut down without stopping the module activity.

* From the standpoint of the PRCM module, a functional clock is distributed directly to the related modules through a dedicated tree. It is identified with an _FCLK suffix.

8.1.3.2 Module-Level Clock Management

Each module in the device may also have specific clock requirements. Certain module clocks must be active when operating in specific modes, or may be gated otherwise. Globally, the activation and gating of the module clocks are managed by the PRCM module. Hence, the PRCM module must be aware of when to activate and when to gate the module clocks. The PRCM module differentiates the clock-management behavior for device modules based on whether the module can initiate transactions on the device interconnect (called master module or initiators) or cannot initiate transactions and only responds to the transactions initiated by the master (called slave module or targets). Thus, two hardware-based power-management protocols are used:

* Master standby protocol: Clock-management protocol between the PRCM and master modules.

* Slave idle protocol: Clock-management protocol between the PRCM and slave modules.

8.1.3.2.1 Master Standby Protocol

8.1.3.2.2 Slave Idle Protocol

8.1.3.3 Clock Domain

8.1.3.3.1 Clock Domain-Level Clock Management

8.1.4 Power Management

8.1.4.1 Power Domain

A power domain is a section (that is, a group of modules) of the device with an independent and dedicated power manager. A power domain can be turned on an off without affecting the other parts of the device.

To minimize device power consumption, the modules are grouped into power domains. A power domain can be split into a logic area and a memory area.

8.1.4.2 Power Domain Management

8.1.4.2.1 Power-Management Techniques

8.1.4.2.1.1 Adaptive Voltage Scaling

8.1.4.3 Power Modes

8.1.4.3.1 Active

8.1.4.3.2 Standby

8.1.4.3.3 Deepsleep 1

8.1.4.3.4 Deepsleep 0

8.1.4.3.5 RTC-Only

8.1.4.3.6 Internal RTC LDO

8.1.4.3.7 Supported Low Power USB Wakeup Scenarios

8.1.4.4 Main Oscillator Control During Deep Sleep

8.1.4.5 Wakeup Sources/Events

8.1.4.6 Functional Sequencing for Power Management with Cortex M3

8.1.4.6.1 Periodic Idling of Cortex A8 MPU

8.1.4.6.2 Sleep Sequencing

8.1.4.6.3 Wakeup Sequencing

8.1.5 PRCM Module Overview

8.1.5.1 Interface Descriptions

8.1.5.1.1 OCP Interfaces

8.1.5.1.2 OCP Slave Interfaces

8.1.5.1.3 Power Control Interface

8.1.5.1.4 Device Control Interface

8.1.5.1.5 Clocks Interface

8.1.5.1.6 Resets Interface

8.1.5.1.7 Modules Power Management Control Interface

8.1.5.1.8 Initiator Modules Interface

8.1.5.1.9 Targets Modules Interface

8.1.6 Clock Generation and Management

8.1.6.1 Terminology

The PRCM produces 2 types of clock:

* Interface clocks: these clocks primarily provide clocking for the system interconnect modules and the portions of device's functional modules which interface to the system interconnect modules. In most cases, the interface clock supplies the functional module's system interconnect interface registers. For some modules, interface clock is also used as functional clock.

* Functional clock: this clock supplies the functional part of a module or a sub-system. In some cases, a module or a subsystem may require several functional clocks: 1 or several main functional clock(s), 1 or several optional clock(s). A module needs its main clock(s) to be operational. Optional clocks are used for specific features and can be shutdown without stopping the module.

8.1.6.2 Clock Structure

The ADPLLS module is used for Core, Display, ARM Subsystem, and DDR PLLs.

The ADPLLLJ module is used for the peripheral functional clocks.

8.1.6.3 ADPLLS

8.1.6.3.1 Clock Functions

8.1.6.4 ADPLLLJ (Low Jitter DPLL)

8.1.6.4.1 Clock Functions

8.1.6.5 M2 and N2 Change On-the-Fly

8.1.6.6 Spread Spectrum Clock (SSC)

8.1.6.7 Core PLL Description

8.1.6.7.1 Core PLL Configuration

8.1.6.8 Peripheral PLL Description

8.1.6.8.1 Configuring the Peripheral PLL

8.1.6.9 MPU PLL Description

8.1.6.9.1 Configuring the MPU PLL

8.1.6.10 Display PLL Description

8.1.6.10.1 Configuring the Display PLL

8.1.6.11 DDR PLL Description

8.1.6.11.1 Configuring the DDR PLL

8.1.6.12 CLKOUT Signals

8.1.6.13 Timer Clock Structure

8.1.7 Reset Management

8.1.8 Power-Up/Down Sequence

8.1.9 IO State

8.1.10 Voltage and Power Domains

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Now, let's find out what does u-boot do by default.

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At arch/arm/cpu/armv7/am33xx/clock_am33xx.c:

void enable_basic_clocks(void)

{

u32 *const clk_domains[] = {

&cmper->l3clkstctrl,

&cmper->l4fwclkstctrl,

&cmper->l3sclkstctrl,

&cmper->l4lsclkstctrl,

&cmwkup->wkclkstctrl,

&cmper->emiffwclkctrl,

&cmrtc->clkstctrl,

0

};

u32 *const clk_modules_explicit_en[] = {

&cmper->l3clkctrl,

&cmper->l4lsclkctrl,

&cmper->l4fwclkctrl,

&cmwkup->wkl4wkclkctrl,

&cmper->l3instrclkctrl,

&cmper->l4hsclkctrl,

&cmwkup->wkgpio0clkctrl,

&cmwkup->wkctrlclkctrl,

&cmper->timer2clkctrl,

&cmper->gpmcclkctrl,

&cmper->elmclkctrl,

&cmper->mmc0clkctrl,

&cmper->mmc1clkctrl,

&cmwkup->wkup_i2c0ctrl,

&cmper->gpio1clkctrl,

&cmper->gpio2clkctrl,

&cmper->gpio3clkctrl,

&cmper->i2c1clkctrl,

&cmper->cpgmac0clkctrl,

&cmper->spi0clkctrl,

&cmrtc->rtcclkctrl,

&cmper->usb0clkctrl,

&cmper->emiffwclkctrl,

&cmper->emifclkctrl,

0

};

do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);

/* Select the Master osc 24 MHZ as Timer2 clock source */

writel(0x1, &cmdpll->clktimer2clk);

}

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And at arch/arm/cpu/armv7/am33xx/clock.c:

static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,

u32 wait_for_enable)

{

clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,

enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);

debug("Enable clock module - %p\n", clkctrl_addr);

// printf("+++ enable_clock_module +++ reg = 0x%x, mode = 0x%x, wait = 0x%x\n",

(uint32_t)clkctrl_addr, enable_mode, wait_for_enable);

if (wait_for_enable)

wait_for_clk_enable(clkctrl_addr);

}

static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)

{

clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,

enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);

debug("Enable clock domain - %p\n", clkctrl_reg);

// printf("+++ enable_clock_domain +++ reg = 0x%x, mode = 0x%x\n",

(uint32_t)clkctrl_reg, enable_mode);

}

void do_enable_clocks(u32 *const *clk_domains,

u32 *const *clk_modules_explicit_en, u8 wait_for_enable)

{

u32 i, max = 100;

/* Put the clock domains in SW_WKUP mode */

for (i = 0; (i < max) && clk_domains[i]; i++) {

enable_clock_domain(clk_domains[i],

CD_CLKCTRL_CLKTRCTRL_SW_WKUP);

}

/* Clock modules that need to be put in SW_EXPLICIT_EN mode */

for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {

enable_clock_module(clk_modules_explicit_en[i],

MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,

wait_for_enable);

};

}

================

Note that the two printf sentences are added by me.

Printf information at ttyO0 console:

+++ enable_clock_domain +++ reg = 0x44e0000c, mode = 0x2

+++ enable_clock_domain +++ reg = 0x44e00008, mode = 0x2

+++ enable_clock_domain +++ reg = 0x44e00004, mode = 0x2

+++ enable_clock_domain +++ reg = 0x44e00000, mode = 0x2

+++ enable_clock_domain +++ reg = 0x44e00400, mode = 0x2

+++ enable_clock_domain +++ reg = 0x44e000d0, mode = 0x2

+++ enable_clock_domain +++ reg = 0x44e00804, mode = 0x2

+++ enable_clock_module +++ reg = 0x44e000e0, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e00060, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e00064, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e0040c, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e000dc, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e00120, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e00408, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e00404, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e00080, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e00030, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e00040, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e0003c, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e000f4, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e004b8, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e000ac, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e000b0, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e000b4, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e00048, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e00014, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e0004c, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e00800, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e0001c, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e000d0, mode = 0x2, wait = 0x1

+++ enable_clock_module +++ reg = 0x44e00028, mode = 0x2, wait = 0x1

Those function means belowactions:

(*0x44e0000c & (~0x03) | 0x02) CM_PER_L3_CLKSTCTRL Register: 0x0000005E

(*0x44e00008 & (~0x03) | 0x02) CM_PER_L4FW_CLKSTCTRL Register: 0x00000102

(*0x44e00004 & (~0x03) | 0x02) CM_PER_L3S_CLKSTCTRL Register: 0x0000000a

(*0x44e00000 & (~0x03) | 0x02) CM_PER_L4LS_CLKSTCTRL Register: 0x03004502

(*0x44e00400 & (~0x03) | 0x02) CM_WKUP_CLKSTCTRL Register: 0x00001e16

(*0x44e00804 & (~0x03) | 0x02) CM_RTC_CLKSTCTRL Register: 0x00000302

Controls the clock state transition of domains.

SW_WKUP: Start a software forced wake-up transition on the domain.

(*0x44e000d0 & (~0x03) | 0x02) CM_PER_EMIF_FW_CLKCTRL Register: 0x00000002

(*0x44e000e0 & (~0x03) | 0x02) CM_PER_L3_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e00060 & (~0x03) | 0x02) CM_PER_L4LS_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e00064 & (~0x03) | 0x02) CM_PER_L4FW_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e0040c & (~0x03) | 0x02) CM_WKUP_L4WKUP_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e000dc & (~0x03) | 0x02) CM_PER_L3_INSTR_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e00120 & (~0x03) | 0x02) CM_PER_L4HS_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e00408 & (~0x03) | 0x02) CM_WKUP_GPIO0_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e00404 & (~0x03) | 0x02) CM_WKUP_CONTROL_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e00080 & (~0x03) | 0x02) CM_PER_TIMER2_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e00030 & (~0x03) | 0x02) CM_PER_GPMC_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e00040 & (~0x03) | 0x02) CM_PER_ELM_CLKCTR Register: 00000002 (Wait for idle)

(*0x44e0003c & (~0x03) | 0x02) CM_PER_MMC0_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e000f4 & (~0x03) | 0x02) CM_PER_MMC1_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e004b8 & (~0x03) | 0x02) CM_WKUP_I2C0_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e000ac & (~0x03) | 0x02) CM_PER_GPIO1_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e000b0 & (~0x03) | 0x02) CM_PER_GPIO2_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e000b4 & (~0x03) | 0x02) CM_PER_GPIO3_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e00048 & (~0x03) | 0x02) CM_PER_I2C1_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e00014 & (~0x03) | 0x02) CM_PER_CPGMAC0_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e0004c & (~0x03) | 0x02) CM_PER_SPI0_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e00800 & (~0x03) | 0x02) CM_RTC_RTC_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e0001c & (~0x03) | 0x02) CM_PER_USB0_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e000d0 & (~0x03) | 0x02) CM_PER_EMIF_FW_CLKCTRL Register: 00000002 (Wait for idle)

(*0x44e00028 & (~0x03) | 0x02) CM_PER_EMIF_CLKCTRL Register: 00000002 (Wait for idle)

Control the way mandatory clocks are managed.

ENABLE: Module is explicitly enabled. Interface clock (if not used for functions) may be gated according to the clock domain state. Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen.

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Here comes to the conclusion:

I have to add LCD's clk settings of clk_domains[] and clk_modules_explicit_en[].

After read this chapter, we can go back to chapter 27, to continue LCD's drivers.