linux64位内核地址空间,64位Linux的内核和用户地址空间

32位的Linux中，0x00000000-0xBFFFFFFFFF 这3GB是 用户空间

0xC00000000-0xFFFFFFFFFF 这1GB是 内核空间

++++++++++++++++++++++++++++++++++++++++++

x86-64

From Wikipedia, the free encyclopedia

(Redirected from )

Jump to:,

"AMD64" and "Intel 64" redirect here. For the Intel 64-bit architecture called IA-64, see .

x86-64 is an extension of the .

It supports vastly larger virtual and physical address spaces than are

possible on x86, thereby allowing programmers to conveniently work with

much larger data sets. x86-64 also provides general purpose registers and numerous other enhancements. The original specification was created by , and has been implemented by AMD, , , and others. It is fully backwards compatible with Intel 16-bit and 32-bit code.(p13-14)

Because the full x86 16-bit and 32-bit instruction sets remains

implemented in hardware without any intervening emulation, existing x86 executables run with no compatibility or performance penalties,

although existing applications that are recoded to take advantage of

new features of the processor design may see performance increases.

AMD's method of extending Intel's x86 32-bit instruction set to be a

subset of its x86-64 instruction set is the same technique Intel

employed to extend its .

Prior to launch, "x86-64" and "x86_64" were used to refer to the instruction set. Upon release, AMD named it AMD64 Intel initially used the names IA-32e and EM64T before finally settling on Intel 64 for their implementation. x86-64 is still used by many in the industry, while others, notably (now ) and , use x64 while the BSD family of OSs use AMD64.

The core was the first to implement the architecture; this was the first significant addition to the architecture designed by a company other than Intel. Intel was forced to follow suit and introduced a modified family which was fully software-compatible with AMD's design and specification. introduced x86-64 in their VIA Isaiah architecture, with the .

The x86-64 specification is distinct from the Intel (formerly IA-64) architecture, which is not compatible on the native instruction set level with the x86 architecture.

Contents

AMD64

AMD64 logo

The AMD64 instruction set is implemented in AMD's , , , , , , , , , , and later processors.

History of AMD64

AMD64 was created as an alternative to the radically different architecture, which was designed by Intel and . Originally announced in 1999 with a full specification in August 2000,

the AMD64 architecture was positioned by AMD from the beginning as an

evolutionary way to add 64-bit computing capabilities to the existing

x86 architecture, as opposed to Intel's approach of creating an entirely

new 64-bit architecture with IA-64.

The first AMD64-based processor, the , was released in April 2003.

Architectural features

The primary defining characteristic of AMD64 is the availability of 64-bit general-purpose , e.g. rax, rbx etc., 64-bit arithmetic and logical operations, and 64-bit . The designers took the opportunity to make other improvements as well. The most significant changes include:

64-bit integer capability: All general-purpose registers (GPRs) are expanded from 32

to 64 bits, and all arithmetic and logical operations,

memory-to-register and register-to-memory operations, etc., can now

operate directly on 64-bit integers. on the are always in 8-byte strides, and are 8 bytes wide.

Additional registers: In addition to increasing the size of

the general-purpose registers, the number of named general-purpose

registers is increased from eight (i.e. eax, ebx, ecx, edx, ebp, esp,

esi, edi) in x86 to 16 (i.e. rax, rbx, rcx, rdx, rbp, rsp, rsi, rdi, r8,

r9, r10, r11, r12, r13, r14, r15). It is therefore possible to keep

more local variables in registers rather than on the stack, and to let

registers hold frequently accessed constants; arguments for small and

fast subroutines may also be passed in registers to a greater extent.

However, AMD64 still has fewer registers than many common ISAs (which typically have 32–64 registers) or -like machines such as the (which has 128 registers); note, however, that because of the number of physical registers is often much larger than the number of registers exposed by the instruction set.

Additional XMM (SSE) registers: Similarly, the number of 128-bit XMM registers (used for instructions) is also increased from 8 to 16.

Larger virtual address space: The AMD64 architecture defines a

64-bit virtual address format, of which the low-order 48 bits are used

in current implementations.(p120) This allows up to 256  (248 )

of virtual address space. The architecture definition allows this limit

to be raised in future implementations to the full 64 bits,(p2)(p3)(p13)(p117)(p120) extending the virtual address space to 16  (264 bytes). This is compared to just 4  (232 bytes) for the x86. This means that very large files can be operated on by

the entire file into the process' address space (which is often much

faster than working with file read/write calls), rather than having to

map regions of the file into and out of the address space.

Larger physical address space: The original implementation of the AMD64 architecture implemented 40-bit physical addresses and so could address up to 1 TB (240 bytes) of RAM.(p24) Current implementations of the AMD64 architecture (starting from ) extend this to 48-bit physical addresses and therefore can address up to 256 TB of RAM. The architecture permits extending this to 52 bits in the future(p24) (limited by the page table entry format);(p131) this would allow addressing of up to 4  of RAM. For comparison, 32-bit x86 processors are limited to 64 GB of RAM in (PAE) mode, or 4 GB of RAM without PAE mode.(p4)

Larger physical address space in legacy mode: When operating in the AMD64 architecture supports

(PAE) mode, as do most current x86 processors, but AMD64 extends PAE

from 36 bits to an architectural limit of 52 bits of physical address.

Any implementation therefore allows the same physical address limit as

under long mode.(p24)

Instruction pointer relative data access: Instructions can now reference data relative to the instruction pointer (RIP register). This makes , as is often used in shared libraries and code loaded at run time, more efficient.

SSE instructions: The original AMD64 architecture adopted Intel's and as core instructions. instructions were added in April 2005. SSE2 is an alternative to the instruction set's

with the choice of either IEEE 32-bit or 64-bit floating-point

mathematics. This provides floating-point operations compatible with

many other modern CPUs. The SSE and SSE2 instructions have also been

extended to operate on the eight new XMM registers. SSE and SSE2 are

available in 32-bit mode in modern x86 processors; however, if they're

used in 32-bit programs, those programs will only work on systems with

processors that have the feature. This is not an issue in 64-bit

programs, as all AMD64 processors have SSE and SSE2, so using S