mysql已死 subsys被锁_解决Linux上安装MYSQL“mysqld 已死,但是 subsys 被锁 ”的方法...

今天在RED HAT 9上面安装了MYSQL,但是在service mysql start以后,查看service mysql status的时候出现以下提示:

mysqld 已死,但是 subsys 被锁

我起初还看了日志文件,日志文件提示:

Cannot initialize InnoDB as 'innodb_data_file_path' is not set.

If you do not want to use transactional InnoDB tables, add a line

skip-innodb

to the [mysqld] section of init parameters in your my.cnf

or my.ini. If you want to use InnoDB tables, add to the [mysqld]

section, for example,

innodb_data_file_path = ibdata1:10M:autoextend

But to get good performance you should adjust for your hardware

the InnoDB startup options listed in section 2 at

http://www.innodb.com/ibman.html

060806 12:51:01 /usr/libexec/mysqld: Incorrect information in file: './mysql/host.frm'

060806 12:51:01 mysqld ended

我感觉日志文件好象不怎么对,说实话对于一个新手来说,我连.cnf文件在哪里都不知道,我后来在MYSQL的论坛里找到了解决方法,至于原理,我还没有漫漫体会,我把原版的英文发给大家看看:

1. Obviously the 'ole check the log file for anything nasty

cat /var/log/mysqld.log

2. Stop the service

service mysqld stop

3. Check to see if the service stopped, it might be calling the wrong pid.

ps aux | grep mysql

4. Kill any mysql process that might still be running.

kill -9 ??? ???

5. (*CAREFUL*) Remove/move/backup any databases from the data directory, only do this step if you need to.

rm -Rf /var/lib/mysql/*

6. Check your global options configuration file, should be similar to stevanbt's initial post.

cat /etc/my.cnf

7. Copy over one of the preconfigured 'sample' server-specific options file. Global (/etc/my.cnf) file has priority over server-specific file, but these have more options in them and have been tuned for a certain role.

cp /usr/share/doc/mysql-server-?.??.??/my-small.cnf /var/lib/mysql

8. Recreate the initial databases, this step is optional as the initscripts will do this anyway.

mysql_install_db

9. Check and set the runlevels for the service.

chkconfig --level 345 mysqld on

chkconfig --list mysqld

10. Start the service.

service mysqld start

11. Check the log file (step 1)

Thats just a basic step through check, most of you have probably already done this.

其实做到step 9问题都已经解决了

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好的,我已经收到了文件。现在为您添加注释: ```verilog module e203_subsys_nice_core( input [31:0] in1, // 输入信号1 input [31:0] in2, // 输入信号2 input [2:0] op_sel, // 操作选择信号 output [31:0] out1, // 输出信号1 output [31:0] out2, // 输出信号2 output [31:0] out3, // 输出信号3 output [31:0] out4 // 输出信号4 ); // 内部信号 reg [31:0] result; // 计算结果 reg [31:0] reg_in1; // 寄存器输入信号1 reg [31:0] reg_in2; // 寄存器输入信号2 reg [1:0] state; // 状态机状态 reg [1:0] next_state; // 下一个状态 reg op_done; // 操作完成标志 reg [2:0] op_count; // 操作计数器 reg stall; // 暂停标志 reg [31:0] reg_in; // 寄存器输入信号 // 状态常量定义 localparam S_IDLE = 2'b00; // 空闲状态 localparam S_OP_A = 2'b01; // 操作输入1状态 localparam S_OP_B = 2'b10; // 操作输入2状态 localparam S_OP_DONE = 2'b11; // 操作完成状态 // 状态机 always @(posedge clk, posedge resetn) begin if (~resetn) begin state <= S_IDLE; op_done <= 0; op_count <= 0; stall <= 0; end else begin state <= next_state; end end // 操作选择 always @(op_sel) begin case (op_sel) 3'b000: reg_in <= reg_in1 + reg_in2; // 加法操作 3'b001: reg_in <= reg_in1 - reg_in2; // 减法操作 3'b010: reg_in <= reg_in1 & reg_in2; // 与操作 3'b011: reg_in <= reg_in1 | reg_in2; // 或操作 3'b100: reg_in <= reg_in1 ^ reg_in2; // 异或操作 3'b101: reg_in <= reg_in1 >> reg_in2; // 右移操作 3'b110: reg_in <= reg_in1 << reg_in2; // 左移操作 3'b111: reg_in <= reg_in1 * reg_in2; // 乘法操作 endcase end // 计算结果 always @(posedge clk, posedge resetn) begin if (~resetn) begin result <= 0; end else begin if (op_done) begin result <= reg_in; end end end // 状态机控制 always @(*) begin next_state = state; stall = 0; case (state) S_IDLE: begin if (op_sel != 3'b000) begin next_state = S_OP_A; end end S_OP_A: begin reg_in1 = in1; reg_in2 = in2; if (op_count < 2) begin next_state = S_OP_B; end else begin next_state = S_OP_DONE; end end S_OP_B: begin reg_in1 = result; if (op_count == 0) begin reg_in2 = in1; end else begin reg_in2 = in2; end next_state = S_OP_A; op_count <= op_count + 1; stall = 1; end S_OP_DONE: begin op_done = 1; next_state = S_IDLE; stall = 1; end endcase end // 输出信号 assign out1 = result; assign out2 = result; assign out3 = result; assign out4 = result; endmodule ``` 注释已经添加在代码中,您可以参考注释理解代码的具体实现。如果您有任何疑问或需要进一步解释,请告诉我。
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