S3C2440A 时钟系统

本文是基于韦东山视频的学习笔记

汇总点这

时钟系统

S3C2440A_UserManual_Rev13.pdf

OVERVIEW
The Clock & Power management block consists of three parts: Clock control, USB control, and Power control.
The Clock control logic in S3C2440A can generate the required clock signals including FCLK for CPU, HCLK for the AHB bus peripherals, and PCLK for the APB bus peripherals.

2440A 可以产生3个时钟：

• CPU的 FCLK
• AHB总线(Advanced High performance Bus)的 HCLK
• APB总线(Advanced Peripheral Bus)的 PCLK

The S3C2440A has two Phase Locked Loops (PLLs): one for FCLK, HCLK, and PCLK, and the other dedicated for USB block (48Mhz). The clock control logic can make slow clocks without PLL and connect/disconnect the clock to each peripheral block by software, which will reduce the power consumption.

2440A有2两锁相环(PLL)，一个用于FCLK，HCLK和PCLK，另一个用于USB模块（48Mhz）。

上图就表示了怎么选择时钟源，然而默认选择OM[3:2] 都是是第一个，因为在硬件原理图，这两个引脚都是接地的。

NOTES:

1. Although the MPLL starts just after a reset, the MPLL output (Mpll) is not used as the system clock until the software writes valid settings to the MPLLCON register. Before this valid setting, the clock from external crystal or EXTCLK source will be used as the system clock directly. Even if the user does not want to change the default value of MPLLCON register, the user should write the same value into MPLLCON register.
2. OM[3:2] is used to determine a test mode when OM[1:0] is 11.

这里第一段最后一句我们得到了一个很重要的信息：不管用户想不想改变默认配置，都需要为MPLLCON register写进数据。我们得到了第一个关键的线索：MPLLCON register必须配置。

文档接下来就是对锁相环的介绍，先跳过。

再往下翻，翻到了时钟控制逻辑，这个重要。

The Clock Control Logic determines the clock source to be used, i.e., the PLL clock (Mpll) or the direct external clock (XTIpll or EXTCLK). When PLL is configured to a new frequency value, the clock control logic disables the
FCLK until the PLL output is stabilized using the PLL locking time. The clock control logic is also activated at power-on reset and wakeup from power-down mode.

当PLL配置的时候，FLCK会停止，直到配置而且稳定。

Power-On Reset (XTIpll)
Figure 7-4 shows the clock behavior during the power-on reset sequence. The crystal oscillator begins oscillation within several milliseconds. When nRESET is released after the stabilization of OSC (XTIpll) clock, the PLL starts to operate according to the default PLL configuration. However, PLL is commonly known to be unstable after power-on reset, so Fin is fed directly to FCLK instead of the Mpll (PLL output) before the software newly configures the PLLCON. Even if the user does not want to change the default value of PLLCON register after reset, the user should write the same value into PLLCON register by software.

这里又说到了一个很重要的信息。当nRESET复位被释放稳定后，PLL一开始是默认配置。

但是！！

PLL在刚上电时是很不稳定的，所以在软件重新配置PLLCON时，Fin信号都是直接送给FCLK的，也就是说不配置就没有PLL。

所以不管用户想不想改变默认配置，都需要为PLLCON register写进数据。这里和第一条线索相呼应。

The PLL restarts the lockup sequence toward the new frequency only after the software configures the PLL with a new frequency. FCLK can be configured as PLL output (Mpll) immediately after lock time.

这里当PLL配置的时候，会有一个锁定时间。

再往下翻，USB总线的先跳过。

FCLK is used by ARM920T.
HCLK is used for AHB bus, which is used by the ARM920T, the memory controller, the interrupt controller, the LCD controller, the DMA and USB host block.
PCLK is used for APB bus, which is used by the peripherals such as WDT, IIS, I2C, PWM timer, MMC interface, ADC, UART, GPIO, RTC and SPI.

The S3C2440A supports selection of Dividing Ratio between FCLK, HLCK and PCLK. This ratio is determined by HDIVN and PDIVN of CLKDIVN control register.

在FCLK,HCLK, PCLK之间有一个分频比，这个分频比由CLKDIVN 里的 HDIVN 和 PDIVN 决定。

NOTES

1. CLKDIVN should be set carefully not to exceed the limit of HCLK and PCLK.
2. If HDIVN is not 0, the CPU bus mode has to be changed from the fast bus mode to the asynchronous bus mode using following instructions(S3C2440 does not support synchronous bus mode).
   MMU_SetAsyncBusMode
   mrc p15,0,r0,c1,c0,0
   orr r0,r0,#R1_nF:OR:R1_iA
   mcr p15,0,r0,c1,c0,0
   If HDIVN is not 0 and the CPU bus mode is the fast bus mode, the CPU will operate by the HCLK.
   This feature can be used to change the CPU frequency as a half or more without affecting the HCLK and PCLK.

这里又有一个重要的信息：如果HDIVN不为0，则必须使用以下指令将CPU总线模式从快速总线模式更改为异步总线模式（S3C2440不支持同步总线模式）。

现在我们来整理一下

我们想要时钟系统正常的运行起来，第一：MPLLCON的配置，第二：HDIVN 和 PDIVN设置分频比，第三：设置为异步总线模式。

看回文档的图7-1

1. OSC晶振或者外部晶振产生信号源，通过OM[3:2]的设置决定信号源。
2. 配置MPLL，设置FCLK的频率
3. 配置HDIVN，设置HCLK的频率
4. 配置PDIVN，设置PCLK的频率

配置2440A的三个时钟，就是这样而已，再看看时序图

寄存器

那如果要配置这样的参数应该怎么配置呢

• FCLK 400MHz
• HCLK 100MHz
• PCLK 50MHz

其实也简单，需要配置的都已经在上文字体标粗。而MPLLCON的配置，文档给出了公式：

MPLL Control Register
Mpll = (2 * m * Fin) / (p * 2 S )
m = (MDIV + 8), p = (PDIV + 2), s = SDIV

这个是FCLK的频率计算方法，但是由于太过复杂，文档也给出了参考参数。

也就是说，把 MDIV 设置为92(0X5C)， PDIV SDIV 设置为1 就可以了。

来看这个PLLCON寄存器
PLLCON寄存器 地址 : 0x4C000004
MDIV [19:12] : 0x5C
PDIV [9:4] : 1
SDIV [1:0] : 1
即：[0x4C000004] = 0b101 1100 0000 0001 0001‬ = 0x5C011

再看CLKDIVN寄存器

要使得 FCLK:HCLK:PCLK = 1:4:8

看图可知
CLKDIVN寄存器 地址：0x4C000014
HDIVN [2:1] : 0b10
PDIVN [0] : 0b1
即：[0x4C000014] = 0b101 = 0x5

至此，两个寄存器设置完毕，最后设置为异步模式便大功告成。

在上一课流水灯的基础上修改代码led.S

.text
.global _start

_start:

	/* 关闭看门狗 */
	ldr r0, =0x53000000
	ldr r1, =0
	str r1, [r0]  /* 把WTCON第零位设置为0，关看门狗 */

	/* 设置为异步模式 */
	mrc p15,0,r0,c1,c0,0
	orr r0,r0,#0xC0000000	//R1_nF:OR:R1_iA
	mcr p15,0,r0,c1,c0,0

	/* 设置CLKDIVN寄存器使得 FCLK:HCLK:PCLK = 1:4:8
	 * CLKDIVN寄存器 地址：0x4C000014
	 * HDIVN [2:1] : 0b10
	 * PDIVN [0] : 0b1
	 * 即：[0x4C000014] = 0b101 = 0x5
	 */
	ldr r0, =0x4C000014
	ldr r1, =0x5
	str r1, [r0]
	
	/* 设置PLLCON使FLCK = 400MHz
	 * PLLCON寄存器 地址 :  0x4C000004
	 * MDIV  [19:12] : 0x5C = 92
	 * PDIV [9:4]	 : 1
	 * SDIV [1:0]    : 1
	 * 即：[0x4C000004] = 0b101 1100 0000 0001 0001‬ = 0x5C011
	 */
	ldr r0, =0x4C000004
	ldr r1, =0x5C011
	str r1, [r0]

	/* 设置sp栈，自动识别nor启动还是nand启动
	 * nor启动时对应nor flash，nand启动时对应片内内存
	 * 在nor flash 写数据时必须有一定格式
	 * 把0写入0地址，再读出来看有没有修改，有修改就是nand启动，没修改就是nor启动
	 */
	 	
	mov r1, #0
	ldr r0, [r1] /* 先把[0]地址的值备份到r0 */
	str r1, [r1] /* 把0写入[0]地址 */
	ldr r2, [r1] /* 再把[0]地址的值读出来 */
	cmp r1,r2    /* 比较 */
	ldr sp, =0x40000000+4096 /* nor启动 */
	moveq sp , #4096 /*nand 启动*/
	streq r0, [r1] /* 恢复数据 */
	
	bl main
	
halt:
	b halt