S3C2440 中CPU 的七种模式

汇总点这

这篇文章你可能不知我所云，请不要担心，我是给自己看的。

OPERATING MODES
ARM920T supports seven modes of operation:
• User (usr): The normal ARM program execution state
• FIQ (fiq): Designed to support a data transfer or channel process
• IRQ (irq): Used for general-purpose interrupt handling
• Supervisor (svc): Protected mode for the operating system
• Abort mode (abt): Entered after a data or instruction prefetch abort
• System (sys): A privileged user mode for the operating system
• Undefined (und): Entered when an undefined instruction is executed

除了第一种模式，其他模式都是特权模式，特权模式都可以编程操作 CPSR 进入其他特权模式。

CPSR（current program status register）
SPSR（Saved Program Status Register）

一般来说，发生中断，CPU会进入异常向量（中断是异常的一种），一般是0x18

CPSR寄存器位4~0的状态，以下图为参考。

Action on Entering an Exception While handling an exception, the
ARM920T does following activities:

1. Preserves the address of the next instruction in the appropriate Link Register. If the exception has been entered from ARM state, then
   the address of the next instruction is copied into the Link Register
   (that is, current PC + 4 or PC + 8 depending on the exception. See
   Table 2-2 on for details). If the exception has been entered from
   THUMB state, then the value written into the Link Register is the
   current PC offset by a value such that the program resumes from the
   correct place on return from the exception. This means that the
   exception handler need not determine which state the exception was
   entered from. For example, in the case of SWI, MOVS PC, R14_svc will
   always return to the next instruction regardless of whether the SWI
   was executed in ARM or THUMB state.
2. Copies the CPSR into the appropriate SPSR
3. Forces the CPSR mode bits to a value which depends on the exception
4. Forces the PC to fetch the next instruction from the relevant exception vector It may also set the interrupt disable flags to
   prevent otherwise unmanageable nestings of exceptions. If the
   processor is in THUMB state when an exception occurs, it will
   automatically switch into ARM state when the PC is loaded with the
   exception vector address.

Action on Leaving an Exception On completion, the exception handler:

1. Moves the Link Register, minus an offset where appropriate, to the PC. (The offset will vary depending on the type of exception.)
2. Copies the SPSR back to the CPSR
3. Clears the interrupt disable flags, if they were set on entry