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创建一个基于MicroBlaze™的视频测试模式发生器 (TPG)的嵌入式视频应用.pdf
MicroBlaze™是一个软核微处理器,具有丰富的、针对嵌入式应用优化的指令集。性能/功能上虽然没有ZYNQ强大,但是在一些控制场合还是能够做到游刃有余,满足您的需求。这些应用包括工业、医疗、汽车、消费类以及通信市场等。
通过创建一个基于MicroBlaze™的视频测试模式发生器 (TPG)的嵌入式视频应用,在HDMI屏幕上显示彩条,为后面视频处理搭好了基础。
2020-08-29
ug1037-vivado-axi-reference-guide
ug1037-vivado-axi-reference-guide
Xilinx adopted the Advanced eXtensible Interface (AXI) protocol for Intellectual Property
(IP) cores beginning with the Xilinx® Spartan®-6 and Virtex®-6 devices. Xilinx continues
the use of the AXI protocol for IP targeting the UltraScale™ architecture, 7 series, and
Zynq®-7000 All Programmable (AP) SoC devices.
This document is intended to: Introduce key concepts of the AXI protocol.
• Give an overview of what Xilinx tools you can use to create AXI-based IP.
• Explain what features of AXI that have been adopted by Xilinx.
• Provide guidance on how to migrate your existing design to AXI
2019-04-25
AXI4-Stream Video IP and System Design Guide
Chapter 1: Introduction
AXI4-Stream Signaling Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 2: System Design Guide
Video Timing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Propagating Video Timing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reset Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input/Output Interfaces - Automatic Delay Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
External Frame Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Multipoint Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Ancillary Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Interlaced Video Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Video Subsystem Software Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Video Subsystem Bandwidth Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Chapter 3: IP Development Guide
IP Parameterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
General IP Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Timing Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Input/Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Buffering Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
READY – VALID Propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Flushing Pipelined Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Propagating SOF and EOL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Interframe Reinitialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Debugging Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Chapter 4: Tool Support
Core Generator and Vivado Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
EDK Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Send FeedbackAXI4-Stream Video IP and System Design 4
UG934 December 10, 2018 www.xilinx.com
Appendix A: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
2019-04-25
SMPTE ST 2082-12:2016
4320-line and 2160-line Source Image and Ancillary Data Mapping for Quad-link 12G-SDI
SMPTE ST 2082-12 defines the mapping of various source images and associated ancillary data into a Quadlink 12 Gb/s [nominal] SDI bit-serial interface.
The general process for creating a quad-link 12G-SDI is illustrated below in Figure 1 and Figure 2. Detailed
definitions of how this process applies to each of the modes defined in the scope follow in other sections of
this document.
2019-04-25
Altera DSP Literature
Part I: DSP DESIGN BUILDING BLOCKS.................................................................................................................................................................... 1
FFT MegaCore Function User Guide....................................................................................................................................................................... 3
CIC Compiler User Guide........................................................................................................................................................................................ 71
NCO Compiler User Guide...................................................................................................................................................................................... 109
FIR Compiler User Guide........................................................................................................................................................................................ 161
Reed-Solomon Compiler User Guide...................................................................................................................................................................... 247
Viterbi Compiler User Guide.................................................................................................................................................................................... 303
Video and Image Processing Suite User Guide...................................................................................................................................................... 369
AN 404: FFT/IFFT Block Floating Point Scaling...................................................................................................................................................... 475
Part II: DSP DEVELOPMENT FLOW - DSP/SOPC BUILDER..................................................................................................................................... 482
DSP Builder User Guide.......................................................................................................................................................................................... 484
DSP Builder Reference Manual............................................................................................................................................................................... 702
FPGAs Provide Reconfigurable DSP Solutions....................................................................................................................................................... 934
Part III: HARDWARE DEVELOPMENT........................................................................................................................................................................ 940
DSP Development Kit, Stratix II Edition Getting Started User Guide....................................................................................................................... 942
DSP Development Kit, Stratix & Stratix Professional Edition Getting Started User Guide...................................................................................... 970
DSP Development Kit, Cyclone II Edition Getting Started User Guide.................................................................................................................... 996
Stratix II EP2S60 DSP Development Board Data Sheet......................................................................................................................................... 1030
Stratix EP1S80 DSP Development Board Data Sheet............................................................................................................................................ 1082
Stratix EP1S25 DSP Development Board Data Sheet............................................................................................................................................ 1130
Cyclone II EP2C35 DSP Development Board Reference Manual........................................................................................................................... 1177
Stratix II EP2S180 DSP Development Board Reference Manual............................................................................................................................ 1287
Part IV: DEVICE SELECTION & ARCHITECTURE...................................................................................................................................................... 1345
DSP Blocks in Stratix & Stratix GX Devices............................................................................................................................................................ 1347
Implementing High-Performance DSP Functions in Stratix & Stratix GX Devices................................................................................................... 1375
DSP Blocks in Stratix II Devices.............................................................................................................................................................................. 1439
DSP Blocks in Stratix III Devices............................................................................................................................................................................. 1473
Stratix II DSP Performance White Paper................................................................................................................................................................. 1523
Embedded Multipliers in Cyclone II Devices............................................................................................................................................................ 1532
Part V: DSP APPLICATIONS USING FPGAS.............................................................................................................................................................. 1542
FPGAs for High-Performance DSP Applications White Paper................................................................................................................................ 1544
Implementing FFT in an FPGA Co-Processor......................................................................................................................................................... 1554
Adaptive Edge Detection for Real-Time Video Processing using FPGAs............................................................................................................... 1562
Direct Up-Conversion using an FPGA-based Polyphase Modem........................................................................................................................... 1572
Extending the Peripheral Set of DSP Processors using FPGAs.............................................................................................................................. 1579
Rapid FPGA Modem Design Techniques for SDRs using Altera DSP Builder........................................................................................................ 1585
FPGA Co-Processing Solutions for High Performance Signal Processing Applications......................................................................................... 1593
Studies on FIR Filter Pre-Emphasis for High-Speed Backplane Data Transmission............................................................................................... 1599
Enabling Real-Time JPEG2000 with FPGA Architectures....................................................................................................................................... 1607
A Simple Data Pre-Distortion Technique for Satellite Communications.................................................................................................................. 1616
Soft Multipliers For DSP Applications...................................................................................................................................................................... 1624
AN 306: Implementing Multipliers in FPGA Devices................................................................................................................................................ 1642
Using PLDs for High-Performance DSP Applications White Paper......................................................................................................................... 1690
High Performance, Low Cost FPGA Correlator for Wideband CDMA & Other Wireless Applications..................................................................... 1696
Versatile Digital QAM Modulator.............................................................................................................................................................................. 1707
Increase Bandwidth in Medical & Industrial Applications With FPGA Co-Processors White Paper........................................................................ 1715
Implementation of CORDIC-Based QRD-RLS Algorithm on Stratix with Embedded Nios Technology................................................................... 1730
Implementing an IEEE Std. 802.16-Compliant FEC Decoder White Paper............................................................................................................. 1740
Implementing OFDM Using Altera Intellectual Property White Paper...................................................................................................................... 1745
Part VI: REFERENCE DESIGNS.................................................................................................................................................................................. 1753
AN 245: Filtering Reference Design Lab................................................................................................................................................................. 1755
AN 263: CORDIC Reference Design....................................................................................................................................................................... 1789
AN 314: Digital Predistortion Reference Design...............................................................................................................................
2019-04-25
EV76C570 2 Mpixels B&W and Color CMOS Image sensor
EV76C570 2 Mpixels B&W and Color CMOS Image sensor data sheet
FEATURES
• 2 million (1600 x 1200) pixels, 4.5 µm square pixels with micro-lens
• Optical format 1/1.8”
• 50 fps@ full resolution
Embedded functions:
• Image Histograms and Context output
• Sub-sampling / binning
• Multi ROI (including 1 line mode)
• Defective pixel correction
• PLL with 5 to 50 MHz input frequency range
• High dynamic range capabilities
• Time to Read improvement (good first image, abort image)
Timing modes:
• Global shutter in serial and overlap modes
• Rolling shutter and Global Reset modes
• Output format 8 or 10 bits parallel plus synchronization
• SPI controls
• Control input pins: Trigger, Reset
• Light control output
• 3.3 V and 1.8 V power supplies
2019-04-25
Quartus Video and Image Processing Suite User Guide
Intel®'s Video and Image Processing (VIP) Suite IP cores are available in the DSP
library of the Intel Quartus® Prime software and may be configured to the required
number of bits per symbols, symbols per pixel, symbols in sequence or parallel and
pixels in parallel.
The VIP Suite offers the following IP cores:
• 2D FIR II Intel FPGA IP
• Avalon-ST Video Monitor Intel FPGA IP (Available only in Platform Designer
(Standard) edition)
• Avalon-ST Video Stream Cleaner Intel FPGA IP
• Chroma Resampler II Intel FPGA IP
• Clipper II Intel FPGA IP
• Clocked Video Input II Intel FPGA IP
• Clocked Video Input Intel FPGA IP (Available only in Platform Designer (Standard)
edition)
• Clocked Video Output II Intel FPGA IP
• Clocked Video Output Intel FPGA IP (Available only in Platform Designer
(Standard) edition)
• Color Plane Sequencer II Intel FPGA IP
• Color Space Converter II Intel FPGA IP
• Configurable Guard Bands Intel FPGA IP
• Control Synchronizer Intel FPGA IP (Available only in Platform Designer (Standard)
edition)
• Deinterlacer II Intel FPGA IP
• Frame Buffer II Intel FPGA IP
• Gamma Corrector II Intel FPGA IP
• Interlacer II Intel FPGA IP
• Mixer II Intel FPGA IP
• Scaler II Intel FPGA IP
• Switch II Intel FPGA IP
• Test Pattern Generator II Intel FPGA IP
• Trace System Intel FPGA IP (Available only in Platform Designer (Standard)
edition)
2019-04-25
3G_SDI_Demo_Board_Xilinx_Version
3G_SDI_Demo_Board_Xilinx_Version
The 3Gb/s SDI Demo Board is designed to demonstrate the functionality, flexibility and
implementation simplicity of Gennum’s 3G/HD/SD SDI devices. The Demo Kit consists
of a 3Gb/s SDI Demo Board, FPGA source code and PC software. Paired with an
additional Xilinx Spartan-3A DSP 1800A Board, it makes a versatile demo/evaluation
platform for Gennum's 3Gb/s products. It is expected to help the users in system design
with Gennum 3Gb/s devices.
The purpose of this document is to describe the functionalities and contents of
Gennum's 3Gb/s SDI Demo Board for the Xilinx Spartan-3A DSP 1800A Board. Also
included are a Quick Start Guide and an Advanced User Guide. If a quick start is
anticipated, Please go to 4.1 Quick Start Guide.
2017-12-29
mingw-w64 GCC for Windows 64 & 32 bits
mingw-w64 GCC for Windows 64 & 32 bits
MinGW_W64_x86_64-6.3.0-release:.exe
2017-04-30
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