ARM指令集

最新推荐文章于 2023-10-29 21:57:29 发布

细嗅蔷薇的猛虎

最新推荐文章于 2023-10-29 21:57:29 发布

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文章标签： ARM

一、指令集汇总

Mnemonic	Instruction	Action
MRC	Move from coprocessor register to CPU register	Rn: = cRn{cRm}
MRS	Move PSR status/flags to register	Rn: = PSR
MSR	Move register to PSR status/flags	PSR: = Rm
MUL	Multiply	Rd: = Rm x Rs
MVN	Move negtive register	Rd: = 0xFFFFFFFF EOR Op2
ORR	OR	Rd: = Rn or Op2
RSB	Reverse subtract	Rd: = Op2 - Rn
RSC	Reserve subtract with Carry	Rd: = Op2 - Rn - 1 + Carry
SBC	Subtract with Carry	Rd: = Rn - Op2 - 1 + Carry
STC	Store coprocessor register to memory	address: = CRn
STM	Store multiple	Stack manipulation(Push)
STR	store register to memory	<address>: = Rd
SUB	Subtract	Rd: = Rn - Op2
SWI	Software interrupt	OS call
SWP	Swap register with memory	Rd: = [Rn],[Rn]: = Rm
TEQ	Test bitwise equality	CPSR flags: = Rn EOR Op2
TST	Test bits	CPSR flags: = Rn and Op2
ADC	Add with carry	Rd: = Rn + Op2 + carry
ADD	Add	Rd: = Rn + Op2
AND	AND	Rd: = Rn AND Op2
B	Branch	R15: = address
BIC	Bit clear	Rd: = Rn AND NOT Op2
BL	Branch with link	R14: = R15,R15 = address
BX	Branch with exchange	R15: = Rn, T bit = Rn[0]
CDP	Coprocessor data processing	(Coprocessor-specific)
CMN	Compare Negtive	CPSR flags: = Rn +Op2
CMP	Compare	CPSR flags: = Rn - Op2
EOR	Exclusive OR	Rd: = (Rn AND NOT Op2) OR (Op2 AND NOT Rn)
LDC	Load coprocessor from memory	Coprocessor load
LDM	Load multiple registers	Stack manipulation(Pop)
LDR	Load register from memory	Rd: = (address)
MCR	Move CPU register to coprocessor register	cRn: = rRn{<op>cRm}
MLA	Multiply accumulate	Rd: = (Rm x Rs) + Rn
MOV	Move register or constant	Rd: = Op2

二、条件域

在ARM状态，所有指令根据CPSR条件代码和指令的条件域条件执行。这个域[bit 31:28]决定了指令在何种环境下执行。如果条件中的C,N,Z,V标志在域中被编码，则指令执行，否则忽略。
有16个条件，缀在助记符后面，由两字符表示。例如，B加EQ为BEQ，表示“等于则跳转”。

Code	Suffix	Flags	Meaning
0000	EQ	Z set	equal
0001	NE	Z clear	not equal
0010	CS	C set	unsigned higher or same
0011	CC	C clear	unsigned lower
0100	MI	N set	negtive
0101	PL	N clear	positive or zero
0110	VS	V set	overflow
0111	VC	V clear	no overflow
1000	HI	C set and Z clear	unsigned higher
1001	LS	C clear or Z set	unsigned lower or same
1010	GE	N equals V	greater or equal
1011	LT	N not equal to V	less than
1100	GT	Z clear AND (N equals V)	greater than
1101	LE	Z set OR (N not equal to V)	less than or equal
1110	AL	(ignored)	always

三、说明

BX {cond} Rn
{cond}----Two character condition mnemonic
Rn ----is an expression evaluating to a valid register number
Examples:
thumb指令置高，跳转到THUMB状态

  ADR    r0,into_THUMB +1     
  BX     r0

跳转目标转为字对齐，跳转到ARM状态

  ADR   R5, Back_to_ARM
  BX    R5

B{L}{cond}<expression>

{L}----Used to request the Branch with Link from fof the instruction.
{cond}----A two-charactor mnemonic of condition field,if absent the AL(always) will be used.
<expression>----The destination.Theassembler calculatesn the offset.
Example

  here    BAL   here    ;Assembles to 0xEAFFFFFE(note effect of PC offset)
          B     there   ;Always condition used as default.
          CMP  R1,#0    ;Compare R1with zero and branch to fred if R1 was zero,otherwise continue.
          
          BEQ   fred     ;Continue to next instruction
          BL    sub+ROM  ;Call subroutine at computed address.
          ADDS   r1,#1   ;Add 1 to register 1,setting CPSR flags on the result then call subroutine if the C flag is clear,
                         ;which will be the case unless R1 held 0xFFFFFFFF.
          BLCC     sub

MOV,MVN(single operand instructions).

<opcode>{cond} Rd,<Op2>
CMP,CMN,TEQ,TST(instructions whitch do not produce a result)

<opcode>{cond} Rn, <Op2>
AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC

<opcode>{cond}{S Rd,Rn,<Op2>

where:
<Op2>----Rm{,<shift>} or,<#expression>
{cond}----A two-charactor condition mnimonic
{S}----Set condition codes if S present(implied for CMP,CMN,TEQ,TST)
<#shift>----<shiftname><register> or <shiftname>#expression,or RRX
(rotate right one bit with extend)
<shiftname>s----ASL,LSL,LSR,ASR,ROR.(ASL is a synonym for
LSL,they assemble to the same code.)

Example:

ADDEQ      R2,R4,R5         ;If the Z flag is set make R2: = R4+R5
 TEQS      R4,#3            ;Test R4 for equality with 3(the S is in fact redundant as the assembler inserts it automatically.)
 SUB       R4,R5,R7,LSR R2  ;Logical right shift R7 by the number in the bottom byte of R2,subtract result from R5,and put the answer into R4.
 MOV       PC,R14           ;Return from subroutine.
 MOVS      PC,R14           ;Return from exception and restore CPSR from SPSR_mode.

MRS - transfer PSR contents to a register
MRS{cond} Rd,<psr>
MSR - transfer register contents to PSR
MSR{cond}<psr>,Rm
MSR - transfer register contents to PSR flag bits only .
MSR{cond}<psrf>,<#expression>

Key:
{cond}----Two-charactor condition mnemonic
Rd and Rm----Expressions evaluating to a register number other than R15
<psr>----CPSR,CPSR_all,SPSR or SPSR_all.
<psrf>----CPSR_flg or SPSR_flg
<#expression> ----Where this is used,the assembler will attempt to generate a shifted immediate 8-bit field to match the expression.If this is impossible,it will give an error.

Examples:

In User mode the instructions behave as follows:

MSR CPSR_all,Rm            ; CPSR[31:28] <- Rm[31:28]
MSR CPSR_flg,Rm            ; CPSR[31:28] <- Rm[31:28]
MSR CPSR_flg,#0xA0000000   ; CPSR[31:28] <- 0xA(set N,C; clear A,V)

In privileged modes the instructions behave as follows:

MSR  CPSR_all,Rm          ; CPSR[31:0] <- Rm[31:0]
MSR  CPSR_flg,Rm          ; CPSR[31:28] <- Rm[31:28]
MSR  CPSR_flg,#0x50000000 ; CPSR[31:28] <- 0x05(set Z,V; clear N,C)
MSR  SPSR_all,Rm          ; SPSR_\<mode>[31:0] <- Rm[31:0]
MSR  SPSR_flg,Rm          ; SPSR_\<mode>[31:28] <- Rm[31:28]
MSR  SPSR_flg,#0xC0000000 ; SPSR_\<mode>[31:28] <- 0xC(set N,Z; clear C,V)
MSR  Rd,SPSR              ; Rd[31:0] <- SPSR_\<mode>[31:0]

MUL{cond} Rd,Rm,Rs
MLA{cond} Rd,Rm,Rs,Rn
{cond}----Two-charactor condition mnimonic
{S}----Set condition codes if S present
Rd,Rm,Rs and Rn----Expressions evaluating to a register number other than R15.

Examples:

MUL R1,R2,R3         ; R1: = R2*R3
MLAEQS  R1,R2,R3,R4  ; Conditionally R1: = R2*R3+R4,Setting condition codes.

UMULL{cond} RdLo, RdHi, Rm, Rs
UMLAL{cond} RdLo, RdHi, Rm, Rs
SMULL{cond} RdLo, RdHi, Rm, Rs
SMLAL{cond} RdLo, RdHi, Rm, Rs

where:
<cond>----Two-charactor condition mneminic.
{S}----Set condition codes if S present
RdLo,RdHi,Rm,Rs----Expressions evaluating to a register number other than R15

Examples:

UMULL R1,R4,R2,R3      ; R4,R1: = R2*R3
UMLALS  R1,R5,R2,R3    ; R5,R1: = R2*R3+R5,R1 also setting condition codes

Single data transfer
<LDR|STR>{cond}{B}{T} Rd,<Address>

where:
LDR----Load from memory into a register
STR----Store from a register into memory
{cond}----Two-character condition mnemonic
{B}----If B is present the byte transfer, otherwise word transfer.
{T}----If T is present the W bit will be set in a post-indexed instruction, forcing non-privileged mode for the transfer cycle. T is not allowed when a pre-indexed addressing moed is specified or implied.
Rd----An expression evaluating to a valid register number
Rn and Rm----Expressions evaluating to a register number. If Rn is R15 the assembler will subtract 8 from the offset value to allow for ARM920T pipelining. In this case base write-back should not be specified.
Example:

STR R1,[R2,R4]!             ; Store R1 at R2+R4(both of which are registers) and write back address to R2

STR R1,[R2],R4              ; Store R1 at R2 and write back R2+R4 to R2
LDR R1,[R2,#16]             ; Load R1 from contents of R2+16,but don't write back
LDR R1,[R2,R3,LSL#2]        ;Load R1 from contents of R2+R3*R4
LDREQB R1,[R6, #5]          ;Conditionally load byte at R6+5 into R1 bits 0 to 7,filling bits 8 to 31 with zeros

STR R1,PLACE                ;Generate PC relative offset to address PLACE
PLACE

LDR   R1,[R2,-R3]!             ;Load R1 from the contents of the halfword address
                               ;contained in R2-R3(both of witch are registers)
                               ;and write back address to R2
 STRH  R3,[R4,#14]             ;Store the halfword in R3 at R14+14 but don't write back
 LDRSB  R8,[R2],#-223          ;Load R8 with the sign extened contents of the byte
                               ;address contained in R2 and write back R2-223 to R2
 LDRNESH  R11,[R0]             ;Conditionally load R11 with the sign extended contents
                               ;of the halfword address contained in R0
 HERE                          ;Generate PC relative offset to address FRED
 STRH   R5,[PC,#(FRED-HERE-8)] ;Store the halfword in R5 at address FRED
 FRED

Block data transfer

<LDM|STM>{cond}<FD|ED|FA|EA|IA|IB|DA|DB> Rn{!},{^}
where
{cond}----Two charactor contition mnemonic
Rn----An expression evaluating to a valid number
----A list of registers and regiter ranges enclosed in {}(e.g.{R0,R2-R7,R10})
{!}----If present requests write-back(w=1),otherwise w=0.
{^}----If present set S bit to load the CPSR along with the PC, or force transfer of user bank when in priviledged mode.
EXAMPLES

LDMFD   SP!,{R0,R1,R2}  ;Unstack 3 registers.
STMIA   R0,{R0-R15}     ;Save all register.
LDMFD   SP!,{R15}       ;R15 <-(SP),CPSR unchenged.
LDMFD   SP!,{R15}^      ;R15 <-(SP),CPSR <- SPSR_mode

STMFD  R13,{R0-R14}^    ;(allowed only in previledge modes).

These instruction may be used to save state on subroutine entry, and restore it efficiently on return to the calling routine:

STMED   SP!,{R0-R3,R14}    ;Save R0 to R3 to use as 
                           ; workspace and R14 for returning.
 BL  somewhere             ;This nested call will overwrite R14
 LDMED   SP!,{R0-R3,R15}   ;Restore workspace and return.

Single data swap

{cond} Rd, Rm, [Rn]
where
{cond}---- Two charactor condition mnemonic
{B}----If B is present then byte transfer, otherwise word transfer.
Rd,Rm,Rn----Expressions evaluating to valid register numbers.
EXAMPLES

SWP     R0,R1,[R2]  ;Load R0 with the word addressed by 
                    ;R2,and Store R1 at R2.
SWPB    R2,R3,[R4]  ;Load R2 with the byte addressed by 
                    ;R4,and store bits 0 to 7 of R3 at R4.
SWPEQ   R0,R0,[R1]  ;Conditionally swap the contents of 
                    ; the word addressed by R1 with R0

Software interrupt

SWI{cond}
EXAMPLES

SWI ReadC     ;Get next charactor from read stream.
SWI Write+"k" ; Output a "k" to the write stream
SWINE 0       ;Conditionally call supervisor with 0 in comment field.

Supervisor code

        0x08 B Supervisor   ;SWI entry point
        Entry Table         ;Addresses of supervisor routines
        DCD ZeroRtn
        DCD ReadCRtn
        DCD WriteRtn
        ...
        Zero    EQU 0
ReadC   EQU 256
Write   EQU 512

       Supervisor               ;SWI has routine required in bits 8-23 and data (if any) in bits 0-7, Assumes R13_svc points to a  suitable satck
       STMFD R13,{R0-R2,R14}    ;Save work registers and return address.
       LDR R0,[R14,#-4]         ;Get SWI instruction
       BIC R0,R0,#0xFF000000    ;Clear top 8 bits
       MOV R1,R0,LSR#8          ;Get routine offset
       ADR R2,EntryTable        ;Get start address of entry table
       LDR R15,[R2,R1,LSL#2]    ;Branch to appropriate routine.
       WriteRtn                 ;Enter with charactor in R0 bits 0-7
       ...
       LDMFD  R13,{R0-R2,R15}^  ;Restore workspace and return ,restoring processor mode and flags.

Coprocessor register transfer

<MCR|MRC>{cond}p#,<expression1>,Rd,cn,cm{,<expression2>}
where:
MRC---- Move from coprocessor to ARM920T register(L=1)
MCR----Move from ARM920T register to coprocessor(L=0)
{cond}----Two character condition mnemonic
p#----the unique number of the required coprocessor
<expression1>----Evaluated to a constant and placed in the CP Opc field
Rd----An expression evaluating to a valid ARM920T register number
cn and cm----Expression evaluating to the valid coprocessor register numbers CRn and CRm respectively
<expression2>----Where present is evaluated to a constant and placed in the CP field
EXAMPLES

MRC     p2,5,R3,c5,c6           ;Request coproc 2 to perform operation 5 on c5 and c6,and transfer the (single 32-bit word) result back to R3
MCR     p6,0,R4,c5,c6           ;Request coproc 6 to perform operation 0 on R4 and place the result in c6.
MRCEQ   p3,9,R3,c5,c6,2         ;Conditionaly request coproc 3 to perform operation 9 (type 2) on c5 and c6,and transfer the result back to R3.

细嗅蔷薇的猛虎

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ARM指令集

一、指令集汇总MnemonicInstructionActionMRCMove from coprocessor register to CPU registerRn: = cRn{cRm}MRSMove PSR status/flags to registerRn: = PSRMSRMove register to PSR status/flags...
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