linux用户态内存屏障,如何使用linux内核中的内存屏障

CPU 1 CPU 2

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{ B = 7; X = 9; Y = 8; C = &Y }

STORE A = 1

STORE B = 2

STORE C = &B LOAD X

STORE D = 4 LOAD C (gets &B)

LOAD *C (reads B)

在没有干预的情况下,CPU 2可以以一些有效的随机顺序感知CPU 1上的事件,尽管CPU 1发出了写屏障:

+-------+ : : : :

| | +------+ +-------+ | Sequence of update

| |------>| B=2 |----- --->| Y->8 | | of perception on

| | : +------+ \ +-------+ | CPU 2

| CPU 1 | : | A=1 | \ --->| C->&Y | V

| | +------+ | +-------+

| | wwwwwwwwwwwwwwww | : :

| | +------+ | : :

| | : | C=&B |--- | : : +-------+

| | : +------+ \ | +-------+ | |

| |------>| D=4 | ----------->| C->&B |------>| |

| | +------+ | +-------+ | |

+-------+ : : | : : | |

| : : | |

| : : | CPU 2 |

| +-------+ | |

Apparently incorrect ---> | | B->7 |------>| |

perception of B (!) | +-------+ | |

| : : | |

| +-------+ | |

The load of X holds ---> \ | X->9 |------>| |

up the maintenance \ +-------+ | |

of coherence of B ----->| B->2 | +-------+

+-------+

: :