rffc2071_RFFC2071 Datasheet(数据表) 6 Page - RF Micro Devices

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RFFC2071/2072

DS140110

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sequence generator. This allows very fine frequency steps and minimizes fractional spurs. The fractional energy is randomized

and appears as fractional noise at frequency offsets above 100kHz which will be attenuated by the loop filter. An external loop

filter is used, giving flexibility in setting loop bandwidth for optimizing phase noise and lock time, for example.

The synthesizer step size is typically 1.5Hz when using a 26MHz reference frequency. The exact step size for any reference and

LO frequency can be calculated using the following formula:

(FREF* P) / (R * 224* LO_DIV)

Where FREFis the reference frequency, R is the reference division ratio, P is the prescalar division ratio, and LO_DIV is the LO

divider value.

Pin 26 (GPO4) can be configured as a lock detect pin. The lock status is also available in the read-back register. The lock detect

function is a window detector on the VCO tuning voltage. The lock flag will be high to show PLL lock which corresponds to the

VCO tuning voltage being within the specified range, typically 0.30V to 1.25V.

The lock time of the PLL will depend on a number of factors; including the loop bandwidth and the reference frequency at the

phase detector. This clock frequency determines the speed at which the state machine and internal calibrations run. A 52MHz

phase detector frequency will give fastest lock times, of typically <50

secs when using the PLL re-lock bit.

Phase Detector and Charge Pump

The phase detector provides a current output to drive an actve loop filter. The charge pump output current is set by the value

contained in the P1_CP_DEF and P2_CP_DEF fields in the loop filter configuration register. The charge pump current is given

by approximately 3

A/bit, and the fields are 6 bits long. This gives default value (31) of 93A and maximum value (63) of

189

A.

If the automatic loop bandwidth calibration is enabled the charge pump current is set by the calibration algorithm based upon

the VCO gain.

The phase detector will operate with a maximum input frequency of 52MHz.

Loop Filter

The active loop filter is implemented using the on-chip low noise op-amp, with external resistors and capacitors. The op-amp

gives a tuning voltage range of typically +0.1V to +2.4V. The internal configuration of the chip is shown below with the recom-

mended active loop filter. The loop filter shown is designed to give lowest integrated phase noise, for reference frequencies of

between 26MHz and 52MHz. The external loop filter components give the flexibility to optimize the loop response for any par-

ticular application and combination of reference and VCO frequencies.

LFILT1

8p2

180p

22K

470R

470R

330p

330p

LFILT2

LFILT3

+1.1V