按照72076文档,使用Vivado 2018.2创建Block Design、使用Petalinux 2018.2配置并生成内核,但板卡系统启动时卡在"bootconsole [cdns0] disabled"处。发现在配置内核时,只要将PCIe PL驱动添加进内核,内核启动时就会卡住。可能是驱动和设备树不匹配。请问有谁知道如何解决?
附件为Xilinx_Answer_72076文档。
PS:以下为Block Design:
以下为内核启动时的log:
Xilinx Zynq MP First Stage Boot Loader
Release 2019.1 May 25 2019 - 07:43:50
NOTICE: ATF running on XCZU7EV/silicon v4/RTL5.1 at 0xfffea000
NOTICE: BL31: Secure code at 0x0
NOTICE: BL31: Non secure code at 0x8000000
NOTICE: BL31: v1.4(release):xilinx-v2018.1-4-g93a69a5a
NOTICE: BL31: Built : 06:50:51, Jun 5 2019
PMUFW: v1.0
U-Boot 2018.01 (Jun 05 2019 - 14:51:40 +0800) Xilinx ZynqMP ZCU102 rev1.0
I2C: ready
DRAM: 4 GiB
usb dr_mode not found
EL Level: EL2
Chip ID: zu7ev
MMC: sdhci@ff170000: 0 (SD)
SF: Detected n25q512a with page size 512 Bytes, erase size 128 KiB, total 128 MiB
*** Warning - bad CRC, using default environment
In: serial@ff000000
Out: serial@ff000000
Err: serial@ff000000
Board: Xilinx ZynqMP
Bootmode: LVL_SHFT_SD_MODE1
Net: ZYNQ GEM: ff0e0000, phyaddr ffffffff, interface rgmii-id
eth0: ethernet@ff0e0000