【电子技术】【2006.09】基于FPGA的异步系统设计与实现_土耳其中东技术大学论文库-CSDN博客

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本文为土耳其中东技术大学（作者：NİZAM AYYILDIZ）的硕士论文，共122页。

现场可编程门阵列（FPGA）广泛应用于数字电路的原型制作。然而，商用FPGA不太适合异步设计。FPGA的体系结构和综合工具大多是为同步设计量身定制的。所以，当异步电路在商用FPGA上实现时，无法观察到潜在的优势。在Xilinx Virtex XCV300系列FPGA上设计了一个以微流水线方式实现的异步算术逻辑单元（ALU）。分析了目标FPGA的危险特性，提出了一种自定时异步电路的设计方法。该设计方法首先设计一个无危险单元集，然后使用关系放置宏（RPM）来保持无危险行为，并采用增量设计技术来组合上层模块而不影响其时序特性。从占用FPGA的逻辑片和数据延迟两个方面对异步ALU的性能进行了评估，并与在同一FPGA上设计的同步ALU进行了比较。

Field Programmable Gate Arrays (FPGAs) are widely used in prototyping digital circuits. However commercial FPGAsare not very suitable for asynchronous design. Both the architecture of the FPGAs and the synthesis tools are mostly tailored to synchronous design. Therefore potential advantages of the asynchronous circuits could not be observed when they areimplemented on commercial FPGAs. This is shown by designing an asynchronousarithmetic logic unit (ALU), implemented in the style of micropipelines, on theXilinx Virtex XCV300 FPGA family. The hazard characteristics of the target FPGAhave been analyzed and a methodology for self-timed asynchronous circuits hasbeen proposed. The design methodology proposes first designing a hazard-free cell set, and then using relationally placed macros (RPMs) to keep the hazard-free behavior, and incremental design technique to combine modules inupper levels without disturbing their timing characteristics. The performanceof the asynchronous ALU has been evaluated in terms of the logic slicesoccupied in the FPGA and data latencies, and a comparison is made with a synchronous ALU designedon the same FPGA.