计算机组成与体系结构(一）

计算机组成与体系结构

第一章：绪论

1.1 计算机组成和计算机体系结构的区别

计算机组成强调控制信号和信号传递方式以及存储器相关(encompassed all physical aspects of computer system)

circuit design,control signal,memory type

how does a computer work

计算机体系结构强调计算机系统的结构和行为(logic aspectsof system implementation as seen by programmer)

instruction sets,instruction format,data type,addressing modes(寻址模式)

how do i design a computer

1.2 计算机主要部件

1. 用于解释和执行程序的处理器（A processor to interpret and execute programs)
2. 一个用于储存数据和程序的存储器(A memory to store both data and program)
3. 一种用于与外部世界传输数据的机制(A mechanism for transferring data to and from the outside world)

principle of equivalence of hardware and software(硬件和软件等价原理)：Anything that can be done with software can also be done with hardware, and anything that can be done with hardware can also be done with software

1.3 the common measure

1. pentium 667MHz：CPU主频

2. SDRAM：旧时代内存：64MB大小，133MHz读写频率（系统总线传输速度）

3. cache：32KB的一级缓存，256KB的二级缓存

4. 30GB EIED hard drive：30GB并行接口硬盘（硬盘转速：7200RPM[主要包括5400PRM]）

5. ports：接口（USB：通用串行接口）

   serial port(串行接口)，parallel（并行接口）

6. PCI接口：外部设备接口（包括声卡，网卡的接口）

10的幂次用来表示功率，电压，频率（计算机时钟速度），位的倍数（bit/s）

2的幂次通常用来表示文件的大小

kbit/s表示1000bits每秒，用小写；KB表示1024B用大写，但也不一定GB可能表示billion

往往10幂次的实际大小小于2的幂次

Hertz : frequency: 1MHz = 1000000Hz

Byte： storage：1KB = 1024 Bytes

主板的结构

南桥：控制硬盘和输入/输出的集成电路

1.4 Standards organizations

The Institute of Electrical and Electronic Engineers (IEEE)

1. Promotes the interests of the worldwide electrical engineering community.
2. Establishes standards for computer components, data representation, and signaling protocols, among many other things.

The International Telecommunications Union (ITU)

Concerns itself with the interoperability of telecommunications systems, including data communications and telephony.

The International Organization for Standardization (ISO)

1. Establishes worldwide standards for everything from screw threads to photographic film
2. Is influential in formulating standards for computer hardware and software, including their methods of manufacture.

1.5 发展历史

机械计算机

电子管计算机

晶体管计算机

集成电路计算机

超大规模集成电路计算机

摩尔定律

硅芯片密度每18个月翻倍

Rock’s law

The cost of capital equipment to build semmiconductor will double every four year

1.6 计算机层次结构

对于计算机来说，每一个层次都是独立的机器：虚拟层

each virtual machine layer is an abstraction of level below(每一层都是下层的抽象)

each layer execute their own instructions calling upon machines at low layer(每一层执行指令时都会调用下层接口)

第六层：用户层：有应用程序组成（User level）：program execution and user interface

第五层：高级语言层(High-Level language level)

第四层：汇编语言层(assembly language level)

第三层：系统软件层：处理操作系统的指令（负责多道程序，存储器保护，进程同步，将汇编语言翻译后不进行修改直接传入）

第二层：指令集架构（ISA）：计算机中特定的体系结构认识的机器语言（能够被电路执行）

第一层：控制层：控制单元确保指令正确解码和执行

控制单元可以由硬接线（控制信号来自数字逻辑模块）和微程序（由硬件能直接执行的机器语言编写而成）

软件硬件等效原则

1.7 冯诺依曼模型

Stored-program computers have become known as von Neumann Architecture systems.

程序储存电脑也被称为冯诺依曼体系结构

1. three hardware systems

   A central processing unit (CPU) with ALU,register and a program counter

   A main memory system

   An I/O system

2. The capacity to carry out sequential instruction processing.（具有执行顺序指令的处理能力）

3. A single data path between the CPU and main memory(von Neumann bottleneck)

   CPU和主存之间存在一个通路

冯诺依曼执行循环

1. The control unit fetces the next instruction from memory using program counter(PC) to determine the location

2. The instruction is decoded into a language that ALU can understand

3. any data operands required to execute the instruction to execute the sinstruction are fetched from main memoyr and placed in the register(从主存当中取出所需要的数据并储存到寄存器当中)

4. The ALU executes the instruction and places the result in the register or memroy

第四章 简单计算机模型

4.1 introduction

4.1.1 CPU basic and organization

function：The computer’s CPU fetches, decodes, and executes program instructions

Two principal parts of CPU are the datapath and control unit

datapath: The datapath consists of an arithmetic-logic unit and storage units (registers)

datapath是多个功能单元的组合：包含了ALU和寄存器，二者被数据总线所连接

control unit: Various CPU components perform sequenced operations according to signals provided by its control unit

提供信号，用于控制顺序执行指令

Register

Registers hold data that can be readily accessed by the CPU

register can be implemented using D flip-flops(触发器）

A 32-bit register requires 32 D flip-flops

ALU（算术逻辑单元）

The arithmetic-logic unit (ALU) carries out logical and arithmetic operations as directed by the control unit

控制单元根据PC寄存器（存储下一条指令的位置）和状态寄存器的储存值来决定进行什么动作

4.1.2 The Bus

CPU通过一条数据总线来和其他的系统组件进行数据共享和交互

定义：A bus is a set of wires that simultaneously convey a single bit along each line

分类：串行总线，并行总线

1. point-to-point bus
2. multipoint bus

分类：Bus consist of data lines,control lines and address lines（根据传输信号的不同）

1. 当data line从一台设备传输bit到另外一台设备的过程中，control line决定数据流的位置以及设备何时可以接入总线
2. address line决定了数据的源头和目的地

point-to-point bus

multipoint bus

category of bus arbitration(总线控制权)

1. daisy chain（菊花链仲裁方式）: permissions are passed from highest-priority device to the lowest

   总线允许信号从最高优先级外设到最低优先级外设，不公平可能高优先级一直不停占用

2. centralized parallel（集中式平行仲裁方式）: each device is directly connected to an arbitration circuit（控制器）

   外设集中向仲裁控制器进行申请，第一个提出申请的外设将得到总线使用权

3. distributed using self-detection（自选则分配式仲裁方式）: devices decide which gets the bus among themselves

   由外设自行检测总线状态，以及自身优先级决定是否使用总线

4. distributed using collision detection（采用冲突检测分配）: any device can try to use the bus, if the data collides(碰撞) with the data of another device, it tries again

   每个设备都允许发出总线使用请求，如果总线检测到冲突，则设备再次发出另一个请求

4.1.3 clocks

时钟被用于同步组件的活动

1. reduce the number of instructions in a program
2. resuce the number of cycles per instruction
3. reduce the number of nanoseconds per clock cycle

4.1.4 I/O subsystem

the computer communciate with outside world through i/o subsystem

1. I/O devices connect to the CPU through various interface

2. I/O can be memory-mapped

   I/O behave like memory from the CPU’s point of view(访问I/O设备的方式和访问内存的方式相同)

3. I/O can be instruction-based

   CPU has a specialized I/O instruction set

4.1.5 Memory organization addressing

memory consist of a linear array of addressable storage cells that are similar to register

存储器是一个数据为的阵列，阵列的每一行的大小和机器的字长相同

memory can be word address or byte address(a word contain two or more bytes)

memory is constructed of RAM chips(内存条) referred to length * width

if the machine is 16bits, a 4M * 16 Ram chip gives 4 megabytes of 16bits memory location

4M can be expressed as 2² * 2²⁰ = 2²² word（word指的是电脑字长长度，地址位置是代表一整个word）

location is numbered as 0 - 2²² -1

所以这个内存至少需要22条地址总线（地址总线要么是on或者off，进行逐个表示内存位置）

physical memory usually consist of more than one RAM chip

example: 4M*16 指的是4M行，每一行都是16-bit； 4M*16的内存空间需要1M*8的内存芯片的数量：

:4M*16/1M*8

构建32words的内存，每个chip都是4words的空间，需要8片chip，需要5根地址总线进行表示

4.1.6 interrupt（中断）

the normal execution of a program is altered when an event of high-priority occurs.

1. I/O request
2. arthimetic error
3. invalid instruction

4.2 Marie

4.2.1 architecture(体系结构)

1. Binary, two‘s complement data representation.

2. Stored program, fixed word length data and instructions.

3. 4K words of word-addressable（字长寻址） main memory.

4. 16-bit data words.

5. 16-bit instructions, 4 for the opcode and 12 for the address.（16位指令系统：4位操作码和12位操作地址）

6. A 16-bit arithmetic logic unit (ALU位宽：算术运算最长处理位数).

7. Seven registers（七个寄存器） for control and data movement

   Accumulator(累加器AC)：存储数据，16-bit register

   memory address register（存储器地址寄存器MAR）：12-bit，内存只有4K（为2的12次方）所以12位足够

   memory buffer register（存储器缓冲寄存器MBR）：在存入内存之前先存储寄存器

   program counter: 12-bit存储下一条指令在内存当中的位置（12位足够）

   instruction register（IR）：存储当前正在执行的指令（不是指令的位置）

   input register（inREG）：8-bit register 保存来自外部输入设备的数据

   output register（outREG）：8-bit register 保存来自外部输入设备的数据

4.2.2 register and buses

the register are interconnected and connected with main memory through data bus

通过数据总线将寄存器和内存进行连接

在MBR到AC之间和MBR和ALU之间存在专用通道：允许MBR的数据直接进行计算，信息从AC流向ALU在回到AC不需要通过总线

4.2.3 instruction set architecture

ISA：specifies the format of instructions and provide opeartions

ISA：计算机软件和硬件之间的接口，模型机的ISA包括13条指令(包括4位操作码，12位地址码)

Load 指令

4.2.4 register transfer notation(寄存器传输表示法)

MARIE的每一条指令都包含了多个microoperations（微操作）

微操作的表示方法（register transfer language）[RTL]

1. notation M[X] to indicate the actual data value stored in memory location X

   取得地址当中存储的值

2. <- to indicate the transfer of bytes to a register or memory location.

MBR和AC之间有内部专用通道，所以AC<-MBR命令行不需要换行，只有需要占用总线的命令才会换行，ALU需要计算所以加法需要换行

指令将存储单元x的内容装到AC寄存器

1. 将地址x放到MAR
2. 将M[MAR]（即MAR存储的地址上的指令）存入MAR的x的地址移动到MBR（缓冲寄存器）
3. 将MRB中的数据存储到AC

4.3 process

4.3.1 fetch-decode-execute cycle（取址，解码，执行）

The fetch-decode-execute cycle is the series of steps that a computer carries out when it runs a program

1. fetch an instruction from memory, and place it into the IR

   从内存当中取出指令，放入IR寄存器（先从PC转移到MAR）

2. in the IR, it is decoded to determine what needs to be done next

   在IR当中指令会被解码（解码操作码和地址码）

3. If a memory value is involved in the operation, it is retrieved and placed into the MBR

   假设包含操作相关的数据，将被转存到MBR内存缓冲寄存器

4. With everything in place, the instruction is executed

PC中的指令可以间接进行改变

4.3.2 interrupts and I/O

Two registers to accommodate input and output

1. input register（输入寄存器） holds data being transferred from an input device into the computer（外部至电脑）
2. the output register（输出寄存器） holds information ready to be sent to an output device.（电脑至外部设备）

Interrupt-driven I/O

1. A signal (interrupt) from the I/O device to the CPU indicating that input or output is complete（I/O设备会给CPU提供中断信号，表明输入输出已完成）
2. Some means of allowing the CPU to detour from the usual fetch-decode-execute cycle to “recognize” this interrupt

4.4 simple program

a set of mnemonic instructions

4.4.1 LOAD 104指令

1. fetch：将PC（存储着下一条指令的地址）的值传递给MAR（存储器地址寄存器）

   100：是指令存在于内存的地址

2. M[MAR]是利用地址取指令本身，将指令本身传递给IR（存储当前指令）

   在解码之后MAR的地址变为104（存储数据的地址）

3. PC++，指向内存的下个地址，即下一条指令

4. 将指令中的地址码[地址代表的内存单元存储着第一个加数]（11-0位）传递给MAR，并且解码操作码（15-12位）

5. 将被加数传递给MBR

6. 将MBR中的数据传递给AC累加器

4.4.2 ADD 105

前四步骤和load 104完全相同，最后一步将MBR和AC的加和传递给AC

4.4.3 store 106

不同在于execute是将AC中的加和传递给MBR，再将MBR传递到M[MAR]

4.5 A Discussion on Assemblers

Assemblers create an object program file from mnemonic source code in two passes

编译器在编译过程中需要扫描两次，分别产生右侧和左侧的表

4.6 Extending Our Instruction Set（扩展指令）

all of the MARIE instructions that we have discussed use a direct addressing mode

指的是直接将内存进行编号，进行访问

indirect addressing, where the address of the address of the operand is given in the instruction

利用指针的形式对内存进行访问

ADDI instruction specifies the address of the address of the operand（间接寻址）

JNS（jump and store)

4.7 A Discussion on Decoding

译码：控制程序执行（hardwired control and microprogrammed control）

1. With microprogrammed control, a small program is placed into read-only memory in the microcontroller（放置在微控制器的用于解码的程序，易于扩展）
2. Hardwired controllers implement this program using digital logic components（组合逻辑设计，难以进行扩展）

4.7.1 Hardwired controllers

our simple system would need a 4-to-14 decoder（解码操作码）

4.7.2 microprogrammed control

the microcode is kept in ROM, PROM, or EPROM firmware

4.8 Real World Architectures

CISC is an acronym for complex instruction set computer（复杂指令集计算机）

RISC stands for reduced instruction set computer（精简指令集计算机）