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关于AXI4的部分总结

This IP core is a cutdown USB host controller which allows communications with full-speed (12mbps) USB devices. The IP is accessed via an AXI4-Lite slave register interface for control, status and data. Data to be sent or received is stored in some internal FIFOs. The data is accessed through the AXI4-Lite slave port. There is no DMA engine (e.g. a bus mastering interface) associated with this IP. The core functions well, is very small, but is fairly inefficient in terms of CPU cycles require

USB2.0协议入门中文版.pdf