时钟通过OM【2 ,3】选择外部时钟还是内部时钟,MPLL和UPLL
MPLL M p s 倍频产生FCLK 和HCLK和PCLK分别作用在CPU和HCLK总线和PCLK总线,
/* 设置MPLL, FCLK : HCLK : PCLK = 400m : 100m : 50m /
/ LOCKTIME(0x4C000000) = 0xFFFFFFFF */ 改变频率后保持多久生效
ldr r0, =0x4C000000
ldr r1, =0xFFFFFFFF
str r1, [r0]
/* CLKDIVN(0x4C000014) = 0X5, tFCLK:tHCLK:tPCLK = 1:4:8 */时钟频率比例
ldr r0, =0x4C000014
ldr r1, =0x5
str r1, [r0]
/* 设置CPU工作于异步模式 */
mrc p15,0,r0,c1,c0,0
orr r0,r0,#0xc0000000 //R1_nF:OR:R1_iA
mcr p15,0,r0,c1,c0,0
设置CPU时钟400MHz
/* 设置MPLLCON(0x4C000004) = (92<<12)|(1<<4)|(1<<0)
* m = MDIV+8 = 92+8=100
* p = PDIV+2 = 1+2 = 3
* s = SDIV = 1
* FCLK = 2mFin/(p2^s) = 210012/(32^1)=400M
*/
ldr r0, =0x4C000004
ldr r1, =(92<<12)|(1<<4)|(1<<0)
str r1, [r0]