数电和Verilog-时序逻辑实例三：计数器

A.16 时序逻辑实例三：计数器

顾名思义，就是用来根据时钟边沿跳变来统计时钟周期数量的模块。

设计模块

//文件路径：a.16/src/counter.v
module counter(clk,rst_n,load_enable,load_counter,dout);
  input clk;
  input rst_n;
  input load_enable;
  input[7:0] load_counter;
  output[7:0] dout;

  reg[7:0] counter;

  always@(posedge clk)begin//当然也可以改为下降沿计数器，只需要把posedge换成negedge即可
    if(!rst_n)
      counter <= 'd0;
    else begin
      if(load_enable)
        counter <= load_counter;
      else
        counter = counter + 1;
    end
  end

  assign dout = counter;

endmodule

测试模块

//文件路径：a.16/sim/testbench/demo_tb.sv
module top;
  logic clk;
  logic rst_n;
  logic load_enable;
  logic[7:0] load_counter;
  logic[7:0] dout;
  
  counter DUT(.clk(clk),.rst_n(rst_n),.load_enable(load_enable),.load_co