可配置siz read_addr and write_addr axi4_full IP

最新推荐文章于 2024-09-23 17:28:28 发布

weixin_44970614

最新推荐文章于 2024-09-23 17:28:28 发布

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分类专栏：笔记文章标签： tcp/ip fpga开发网络协议

本文链接：https://blog.csdn.net/weixin_44970614/article/details/122191498

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本文深入探讨了AXI4-Full接口中可配置的read_addr和write_addr，阐述了它们在网络协议和FPGA开发中的关键作用，详细解释了如何在TCP/IP通信中有效地使用这些地址。

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`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/12/19 10:57:17
// Design Name: 
// Module Name: ufo_compute_ip
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module ufo_compute_ip#
(
    parameter brust_len=16
)
(
    input clk,
    input rst_n,
    
    input [31:0] rd_data,
    output reg [31:0] wr_data,
    
    input M_AXI_WVALID0,
    input M_AXI_WREADY,
    input M_AXI_RVALID,
    input M_AXI_RREADY0,
    
    input [7:0]read_burst_len,
    input [7:0]write_burst_len,
    
    input compute_start,
    output compute_done
    
    );

integer      i ;
reg [31:0] compute_data [0:brust_len-1];
reg [7:0]RD_CNT;
reg [7:0]WR_CNT;
reg co_done;
assign compute_done=co_done;
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        co_done<=1'b0;
    else if(compute_start)
        co_done<=1'b1;
    else 
        co_done<=1'b0;
    
end



always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        RD_CNT<=8'd0;
    else if(M_AXI_RVALID && M_AXI_RREADY0)begin
        if(RD_CNT==read_burst_len-1)
            RD_CNT<=8'd0;
        else
            RD_CNT<=RD_CNT+1'b1;
    end
end



always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        for(i=0;i<16;i=i+1)
            compute_data[i]<=32'd0;
    end
    else if(M_AXI_RVALID && M_AXI_RREADY0)
        compute_data[RD_CNT]<=rd_data;
    
     
end    


 always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        WR_CNT<=8'd0;
    else if(M_AXI_WVALID0 && M_AXI_WREADY)begin
        if(WR_CNT==(write_burst_len-1))
            WR_CNT<=8'd0;
        else
            WR_CNT<=WR_CNT+1'b1;
    end
end
//always@(posedge clk or negedge rst_n)begin
//    if(!rst_n)
//        wr_data<=32'd0;
//    else if(M_AXI_WVALID0 )
//        wr_data<=compute_data[WR_CNT]+5;
//    else
//        wr_data<=32'd0;
//end    
always@(*)begin
    if(!rst_n)
        wr_data=32'd0;
    else if(M_AXI_WVALID0)
        wr_data=compute_data[WR_CNT]+5;
    else
        wr_data=32'd0;
end  
endmodule

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/12/15 13:28:56
// Design Name: 
// Module Name: ufo_wr_ip
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module ufo_wr_ip#
(
    parameter C_AXI_DATA_WIDTH=32,
    parameter C_M_AXI_ID_WIDTH=4
)
(

    input clk,
    input rst_n,
//AW channel
    output [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_AWID,
    output [32-1 : 0] M_AXI_AWADDR,
    output [7    : 0] M_AXI_AWLEN,
    output [2 : 0] M_AXI_AWSIZE,//=clogb2((`AXI_DATA_WIDTH/8)-1);
    output [1 : 0] M_AXI_AWBURST,//=2'b01;
    output  M_AXI_AWLOCK,//1'b0;
    output [3 : 0] M_AXI_AWCACHE,//=4'b0010
    output [2 : 0] M_AXI_AWPROT,//=3'h0;
    output [3 : 0] M_AXI_AWQOS,//=4'h0;
    output  M_AXI_AWVALID,
    input  M_AXI_AWREADY,
    
    //Wr channel
    output [C_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,
    output [C_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,
    output  M_AXI_WLAST0,
    output  M_AXI_WVALID0,
    input  M_AXI_WREADY,
    
    //Resp channel
    input [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_BID,//ignore
    input [1 : 0] M_AXI_BRESP,//ignore
    input  M_AXI_BVALID,//Bvalid and Bread means a a write response.
    output  M_AXI_BREADY,//Bvalid and Bread means a a write response.
    //othoer 
    
    input write_start,
    input [C_AXI_DATA_WIDTH-1 : 0] wdata_current,
    input [7:0] wr_burst_len,
    input [31:0] wr_addr_current

    );
    
    
function integer clogb2 (input integer bit_depth);              
begin                                                           
for(clogb2=0; bit_depth>0; clogb2=clogb2+1)                   
  bit_depth = bit_depth >> 1;                                 
end                                                           
endfunction  
assign M_AXI_WDATA=wdata_current;
assign M_AXI_AWID=0;
assign M_AXI_AWSIZE=clogb2((C_AXI_DATA_WIDTH/8)-1);
assign M_AXI_AWBURST=2'b01;
assign M_AXI_AWLOCK=1'b0;
assign M_AXI_AWCACHE=4'b0010;
assign M_AXI_AWPROT=3'h0;
assign M_AXI_AWQOS=4'h0;
assign M_AXI_WSTRB={
   (C_AXI_DATA_WIDTH/8){
   1'b1}};
    
    
//resp channel    M_AXI_BREADY
reg bready;
assign M_AXI_BREADY=bready;
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        bready<=1'b0;
    else begin
        if(M_AXI_AWVALID && M_AXI_AWREADY)
            bready<=1'b1;
        else if(M_AXI_BREADY && M_AXI_BVALID)
            bready<=1'b0;
    end
end 
    
 //AW channel   
 
reg write_start1;
reg write_start2;
wire pose_write_satr;
assign pose_write_satr=write_start1&(~write_start2);
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        write_start1<=1'b0;
        write_start2<=1'b0;
    end
    else 
        {
   write_start2,write_start1}<={
   write_start1,write_start};
end
//    M_AXI_AWVALID
reg awvalid;
assign M_AXI_AWVALID=awvalid;
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        awvalid<=1'b0;
    else if(pose_write_satr)
        awvalid<=1'b1;
    else if(M_AXI_AWVALID && M_AXI_AWREADY)
        awvalid<=