HDLbits---Fsm serial

HDLbits—Fsm serial

题目比较容易，题目中的in信号包含了一个起始位（0），8个数据位和一个停止位（1），开始in为1，也就是S0状态，当in为0是，进入S1状态，然后经过8个周期进入S2，如果in为1，进入第二轮S0状态.否则进入S3状态，接着如果in为1，回到S0状态，否则保持S3状态。一开始没有考虑没有达到预期的状态，后来增加了一个状态才成功了。

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 
    parameter S0 = 2'd0,S1= 2'd1,S2= 2'd2,S3 = 2'd3;//S0起始状态，当in拉低时，到S1状态
    												//S1计数状态，记满8bit，到S2状态
    												//S2停止状态，如果在预期的情况下没有出现停止位，则FSM必须等待直到找到停止位，然后再尝试接收下一个字节。	
    												//S3停摆状态，没有接收到停止位，done拉低，当in拉高时，跳转到起始状态
    reg[1:0] state,next_state;
    reg [3:0] counter;
    always@(posedge clk)begin
        if(reset)begin
            state = S0;
        end//reste
        else begin
            state = next_state;
        end//else
    end
    
    
    always@(*)begin
        case(state)
            S0:begin
                if(!in)begin
                    next_state = S1;
                end//in = 0
                else begin
                    next_state = S0;
                end//in = 1
            end
            S1:begin
                if(counter == 7)begin
                    next_state = S2;
                end//记满8bit
                else begin
                    next_state = S1;
                end  
            end
            S2:begin
                if(in)begin
                    next_state = S0;
                end//in = 1
                else begin
                    next_state = S3;
                end//in = 0
            end
            S3:begin
                if(in)begin
                    next_state = S0;
                end//in = 1
                else begin
                    next_state = S3;
                end//in = 0
            end
            default:next_state = S0;
        endcase
    end
    
    always@(posedge clk)begin
        case(state)
            S0:begin
                counter <= 0; 
                done <=0 ;
            end
            S1:begin
                counter <= counter + 1;
            end
            S2:begin
                counter <=0;
                if(in)begin
                    done <= 1;
                end//停止位
                else begin
                    done <= 0;
                end
            end
            S3:begin
                counter <=0;
                done <= 0;
            end
            default:begin
                counter <= 0; 
                done <=0 ;
            end
        endcase
    end
endmodule