FPGA入门学习笔记（四）Vivado设计跑马灯

仿真结果

设计文件程序

Method_1

module led_run(
    input Clk,
    input Reset_n,
    output reg [7:0]Led
);
	parameter MCNT = 25'd24999999;
    reg [25:0] counter;
    always@(posedge Clk or negedge Reset_n)begin
        if (!Reset_n)
            counter <= 0;
        else if (counter == MCNT)
            counter <= 0;
        else
            counter <= counter + 1'd1;
    end
    always@(posedge Clk or negedge Reset_n)begin
        if (!Reset_n)
            Led <= 8'b0000_0001;
        else if (counter == MCNT)begin
// Method one
//            if (Led == 8'b1000_0000)
//                Led <= 8'b0000_0001;
//            else
//                Led <= Led << 1;

// Method two
            Led <= {Led[6:0],Led[7]};

            end
        else
            Led <= Led;
    end
endmodule

Method_2

module led_run2(
    input Clk,
    input Reset_n,
    output [7:0]Led
);
	parameter MCNT = 25'd24999999;
    reg [24:0] counter;
    always@(posedge Clk or negedge Reset_n)begin
        if (!Reset_n)
            counter <= 0;
        else if (counter == MCNT)
            counter <= 0;
        else
            counter <= counter + 1'b1;
    end
    
    reg [2:0] counter2;
    always@(posedge Clk or negedge Reset_n)begin
        if (!Reset_n)
            counter2 <= 0;
        else if (counter == MCNT)
            counter2 <= counter2 + 1'b1;
    end
            
    decoder_3_8 decode38(
            .a(counter2[2]),
            .b(counter2[1]),
            .c(counter2[0]),
            .out(Led)
        );
endmodule

仿真文件程序

`timescale 1ns/1ns

module led_run_td();
    reg Clk;
    reg Reset_n;
    wire  [7:0] Led;
    
    led_run2
   // #(
   //	.MCNT(24999)
   //)
	led_run_test(
        .Clk(Clk),
        .Reset_n(Reset_n),
        .Led(Led)
    );
    // 仿真参数重定义，不影响实际模块参数
	defparam led_run_test.MCNT = 25'd24999;
	
    initial Clk <= 1;
    always #10  Clk <= !Clk;
    initial begin
        Reset_n <= 0;
        #200;
        Reset_n <= 1;
        #200000;
    end
endmodule