题目描述
See also: State transition logic for this FSM
The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include an asynchronous reset that resets the FSM to state A.
代码
module top_module(
input clk,
input in,
input areset,
output out); //
parameter A=0,B=1,C=2,D=3;
reg[1:0] next_state,state;
// State transition logic
always@(*)
case(state)
A: next_state=(in==1)?B:A;
B: next_state=(in==1)?B:C;
C: next_state=(in==1)?D:A;
D: next_state=(in==1)?B:C;
endcase
// State flip-flops with asynchronous reset
always@(posedge clk or posedge areset)
if(areset)
state<=A;
else
state<=next_state;
// Output logic
assign out = (state==D);
endmodule