Verilog刷题HDLBits——Tb/tff

题目描述

You are given a T flip-flop module with the following declaration:

module tff (
    input clk,
    input reset,   // active-high synchronous reset
    input t,       // toggle
    output q
);

Write a testbench that instantiates one tff and will reset the T flip-flop then toggle it to the “1” state.

代码

module top_module ();
    reg clk,reset,t;
    wire q;
    
    initial
        begin
            clk=0;
            reset=1;
            t=0;
            #10 reset=0;
            	t=1;
        end
    always #5 clk=~clk;
    
    tff tff(clk,reset,t,q);

endmodule

结果