欢迎kdown编辑器

module  uart_tx(
        input                   clk                             ,//50M   ===>25M
        input                   rst_n                           ,
        input         [ 7: 0]   data_byte                       ,
        input                   send_en                         ,
        input         [ 3: 0]   baud_set                        ,
        output  reg             rs232_tx                        ,
        output  reg             tx_done                         ,
        output  wire            uart_state 
);
	//======================================================================\
	//************** Define Parameter and Internal Signals *****************
	//======================================================================/
	localparam                      BEGIN_BIT       =   1'b0        ;
	localparam                      STOP_BIT        =   1'b1        ;
	localparam                      DATA_BITS       =   10          ;
	localparam                      BAUD_RATE_9600  =   5208        ;
	localparam                      BAUD_RATE_19200 =   2604        ;
	localparam                      BAUD_RATE_38400 =   1302        ;
	localparam                      BAUD_RATE_115200=   434         ;

	reg     [12: 0]                 BAUD_RATE                       ;

	reg                             bps_clk                         ;
	reg     [ 7: 0]                 data_byte_reg                   ;

	reg                             flag_send                       ;

	wire    [10: 0]                 tx_data_temp                    ;

	reg     [19: 0]                 cnt0                            ;
	wire                            add_cnt0                        ;
	wire                            end_cnt0                        ;

	reg     [ 3: 0]                 cnt1                            ;
	wire                            add_cnt1                        ;
	wire                            end_cnt1                        ;



	//======================================================================\
	//**************************** Main Code *******************************
	//======================================================================/
	//data_byte_reg,寄存data_byte
	always  @(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			data_byte_reg   <=  8'd0;
		end
		else if(send_en)begin
			data_byte_reg   <=  data_byte;
		end
	end

	//BAUD_RATE
	always  @(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			BAUD_RATE   <= BAUD_RATE_9600; 
		end
		else begin
			case(baud_set)
				4'd0:   BAUD_RATE   <= BAUD_RATE_9600;
				4'd1:   BAUD_RATE   <= BAUD_RATE_19200;
				4'd2:   BAUD_RATE   <= BAUD_RATE_38400;
				4'd3:   BAUD_RATE   <= BAUD_RATE_115200;
				default:BAUD_RATE   <= BAUD_RATE_9600;
			endcase
		end
	end

	//flag_send
	always  @(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			flag_send   <=  1'b0;
		end
		else if(send_en)begin
			flag_send   <=  1'b1;
		end
		else if(tx_done)begin
			flag_send   <=  1'b0;
		end
	end

	//cnt0
	always @(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			cnt0 <= 0;
		end
		else if(add_cnt0)begin
			if(end_cnt0)
				cnt0 <= 0;
			else
				cnt0 <= cnt0 + 1;
		end
		else begin
			cnt0 <= 0;
		end
	end

	assign  add_cnt0        =       flag_send;
	assign  end_cnt0        =       add_cnt0 && cnt0 == BAUD_RATE-1;

	//cnt1
	always @(posedge clk or negedge rst_n)begin 
		if(!rst_n)begin
			cnt1 <= 0;
		end
		else if(add_cnt1)begin
			if(end_cnt1)
				cnt1 <= 0;
			else
				cnt1 <= cnt1 + 1;
		end
	end

	assign  add_cnt1        =       end_cnt0;
	assign  end_cnt1        =       add_cnt1 && cnt1 == DATA_BITS-1;

	//tx_done
	always  @(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			tx_done <=  1'b0;
		end
		else if(end_cnt1)begin
			tx_done <=  1'b1;
		end
		else begin
			tx_done <=  1'b0;
		end
	end

	//bps_clk
	always  @(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			bps_clk <=  1'b0;
		end
		else if(cnt0 == 1'b1)begin
			bps_clk <=  1'b1;
		end
		else begin
			bps_clk <=  1'b0;
		end
	end

	//tx_data_temp
	assign  tx_data_temp    =   {STOP_BIT, data_byte_reg, BEGIN_BIT };

	//rs232_tx 串行发送数据
	always  @(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			rs232_tx    <=  1'b1;
		end
		else if(flag_send && bps_clk)begin
			rs232_tx    <=  tx_data_temp[cnt1]; 
		end
		else if(!flag_send)begin
			rs232_tx    <=  1'b1;
		end
	end

	//uart_state
	assign  uart_state  =   flag_send;

endmodule






/*
module Uart_tx(
		//----system signal------
		Clk,
		Rst_n,
		//-----------------------
		Tx_trig,
		Tx_data,
		Rs232_tx
	);
		input Clk,Rst_n;
		input Tx_trig;//发送数据开始信号，只有当这个信号出现一个高电平，整个模块才开始工作。
		input [7:0] Tx_data;//需要发送的数据
		

		output reg Rs232_tx;

		reg [ 7:0] tx_data_reg;//数据寄存器，当需要发送的数据送到时，先将其存储在此寄存器中，再进行按位发送
		reg tx_flag;//处于发送状态的标志信号，当tx_flag为高电平，则表示总线上正在发送数据
		reg [12:0] baud_cnt;//波特率计数寄存器
		reg bit_flag;//发送完一位数据标志信号，每当一位数据发送完毕，该信号变为高电平
		reg [ 3:0] bit_cnt;//发送数据位数寄存器，当8位数据发送完毕，寄存器清零

	//tx_data_reg
		always @ (posedge Clk or negedge Rst_n)
		begin
			if(!Rst_n)
				tx_data_reg <= 8’d0;
			else if(Tx_trig == 1’b1 && tx_flag == 1’b0)
				tx_data_reg <= Tx_data;
			else
				tx_data_reg <= tx_data_reg;
		end

	//tx_flag
		always @ (posedge Clk or negedge Rst_n)
		begin
			if(!Rst_n)
				tx_flag <= 1’b0;
			else if(Tx_trig == 1’b1)
				tx_flag <= 1’b1;
			else if(bit_flag == 1’b1 && bit_cnt == 4’d8)
				tx_flag <= 1’b0;
		end

	//baud_cnt
		always @ (posedge Clk or negedge Rst_n)
		begin
			if(!Rst_n)
				baud_cnt <= 13’d0;
			else if(baud_cnt == 13’d5207)
				baud_cnt <= 13’d0;
			else if(tx_flag == 1’b1)
				baud_cnt <= baud_cnt + 1’d1;
			else
				baud_cnt <= 13’d0;
		end

	 //bit_flag
		always @ (posedge Clk or negedge Rst_n)
		begin
			if(!Rst_n)
				bit_flag <= 1’b0;
			else if(baud_cnt == 13’d5207)
				bit_flag <= 1’b1;
			else
				bit_flag <= 1’b0;
		end

	//bit_cnt
		always @ (posedge Clk or negedge Rst_n)
		beg 	
			if(!Rst_n)
				bit_cnt <= 4’d0;
			else if(bit_cnt == 4’d8 && bit_flag == 1’b1)
				bit_cnt <= 4’d0;
			else if(bit_flag == 1’b1)
				bit_cnt <= bit_cnt + 1’b1;
			// else
			// bit_cnt <= bit_cnt;
		end

	//Rs232_tx 
		always @ (posedge Clk or negedge Rst_n)  //产生RS232_tx信号，总线空闲时，该信号为高电平，在bit_cnt为0时，产生一个低电平起始位，
		begin
			if(!Rst_n)                                //紧接着，当bit_cnt分别为1-8时，发送数据的0-7位。其余情况，RS232_tx信号均为高电平
				Rs232_tx <= 1;
			else if(tx_flag == 1)
				case(bit_cnt)
					0: Rs232_tx <= 1’b0;
					1: Rs232_tx <= tx_data_reg[0];
					2: Rs232_tx <= tx_data_reg[1];
					3: Rs232_tx <= tx_data_reg[2];
					4: Rs232_tx <= tx_data_reg[3];
					5: Rs232_tx <= tx_data_reg[4];
					6: Rs232_tx <= tx_data_reg[5];
					7: Rs232_tx <= tx_data_reg[6];
					8: Rs232_tx <= tx_data_reg[7];
					default:Rs232_tx <= 1’b1;
				endcase
			else
				Rs232_tx <= 1’b1;
		end
endmodule
*/