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最新推荐文章于 2024-11-07 23:24:32 发布

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最新推荐文章于 2024-11-07 23:24:32 发布

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分类专栏：笔记文章标签： c语言

本文链接：https://blog.csdn.net/weixin_47192018/article/details/121711191

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Verilog HDL 状态机自动售货机硬件描述语言测试 bench

关键词由CSDN通过智能技术生成

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在这里插入代码片 写出Verilog HDL源程序和测试程序。

auto_sell.v

module auto_sell(five_jiao, one_yuan, clk, reset, sell, five_jiao_out);

 

input five_jiao, one_yuan;

input clk, reset;

output sell, five_jiao_out;

reg sell, five_jiao_out;

reg [2:0] current_state;

reg [2:0] next_state;

 

`define   STATUS0          3'b000

`define   STATUS1          3'b001

`define   STATUS2          3'b011

`define   STATUS3          3'b010

`define   STATUS4          3'b110

`define   STATUS5          3'b111     

`define   STATUS6          3'b101

 

always @ (posedge clk)   

      begin

            current_state = next_state;

      end

always @ (current_state or reset or five_jiao or one_yuan)

begin

      if (!reset)  

            begin

                  next_state = `STATUS0;

                  five_jiao_out = 0; sell=0;

          end

      else   

case (current_state)

      `STATUS0: 

            begin

                  five_jiao_out = 0;      sell=0;

                  if (five_jiao)          next_state = `STATUS1;

                  else  if (one_yuan)     next_state = `STATUS2;

                  else                    next_state = `STATUS0;

            end 

      `STATUS1:  

            begin

                  five_jiao_out = 0;   sell=0;

                  if (five_jiao)          next_state = `STATUS2;

                  else  if (one_yuan)     next_state = `STATUS3;

                  else                    next_state = `STATUS1;

            end

      `STATUS2:  

            begin 

                  five_jiao_out = 0;      sell=0;

                  if (five_jiao)          next_state = `STATUS3;

                  else  if (one_yuan)     next_state = `STATUS4;

                  else                    next_state = `STATUS2;

            end

      `STATUS3: 

          begin 

                  five_jiao_out = 0;   sell=0;

                  if (five_jiao)          next_state = `STATUS4;

                  else  if (one_yuan)     next_state = `STATUS5;   

                  else                 next_state = `STATUS3;          

            end

      `STATUS4:  

          begin 

                  five_jiao_out = 0;      sell=0;

                  if (five_jiao)          next_state = `STATUS5;

                  else  if (one_yuan)     next_state = `STATUS6;

                  else                    next_state = `STATUS4;

            end  

      `STATUS5:  

            begin

                  sell=1;   five_jiao_out=0;

                  if (five_jiao)              next_state=`STATUS1;

                  else  if ( one_yuan )         next_state = `STATUS2;

                  else                       next_state=`STATUS0;

            end 

      `STATUS6: 

            begin 

                  sell=1;

                  if (five_jiao) 

                      begin

                              next_state=`STATUS2;

                              five_jiao_out=0;

                        end

                  else  if ( one_yuan )

                        begin

                           next_state = `STATUS3;

                           five_jiao_out = 0;

                        end 

                  else  begin

                           next_state=`STATUS0;

                           five_jiao_out=1;

                        end 

            end   

      default:

            begin

                  next_state=`STATUS0;  

                  sell=0;

                  five_jiao_out=0;

            end          

      endcase

end

endmodule

 

auto_sell_tb.v

`timescale 1ns/100ps

 

module auto_sell_tb;

    reg five_jiao,one_yuan;

    reg clk, reset;

    wire sell, five_jiao_out;

    wire [2:0] current_state;

    wire [2:0] next_state;

 

    initial begin

        #0.5 reset = 0;

        #5.5 reset = 1;

        #2.0;

    end

    initial begin

        clk=0;

        #0.5 five_jiao = 1; one_yuan = 1;

        #4.0;

 

 

        #2.0 five_jiao = 0; one_yuan = 1;

        #2.0 five_jiao = 0; one_yuan = 1;

        #2.0 five_jiao = 0; one_yuan = 1;

        #2.0 five_jiao = 0; one_yuan = 0;

        #4.0;

   

 

        #2.0 five_jiao = 1; one_yuan = 0;

        #2.0 five_jiao = 1; one_yuan = 0;

        #2.0 five_jiao = 1; one_yuan = 0;

        #2.0 five_jiao = 1; one_yuan = 0;

        #2.0 five_jiao = 1; one_yuan = 0;

        #2.0 five_jiao = 0; one_yuan = 0;

        #4.0;

   

   

        #2.0 five_jiao = 1; one_yuan = 0;

        #2.0 five_jiao = 0; one_yuan = 1;

        #2.0 five_jiao = 1; one_yuan = 0;

        #2.0 five_jiao = 0; one_yuan = 1;

        #2.0 five_jiao = 0; one_yuan = 0;

        #4.0;

   

   

        #2.0 five_jiao = 0; one_yuan = 1;

        #2.0 five_jiao = 1; one_yuan = 0;

        #2.0 five_jiao = 0; one_yuan = 1;

        #2.0 five_jiao = 0; one_yuan = 0;

        #4.0;

   

   

        $stop;

        #1000;

        $finish;

    end

 

    always #1 clk=~clk;

 

    auto_sell auto_sell_test(

        .five_jiao(five_jiao),

        .one_yuan(one_yuan),

        .clk(clk),

        .reset(reset),

        .sell(sell),

        .five_jiao_out(five_jiao_out)

    );

    initial begin

        $dumpfile("auto_sell_test.vcd");

        $dumpvars(0, auto_sell_test);

    end

endmodule

 

auto_sell_test.sh

iverilog -o auto_sell_test auto_sell.v auto_sell_tb.v

vvp -n auto_sell_test -lxt2

cp auto_sell_test.vcd auto_sell_test.lxt

gtkwave auto_sell_test.lxt