FPGA_Hdlbits刷题

准新生

于 2024-06-14 10:25:30 发布

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文章标签： fpga开发

本文链接：https://blog.csdn.net/weixin_49918326/article/details/139674624

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1原题

2代码：


module top_module(
    input in,
    input [9:0] state,
    output [9:0] next_state,
    output out1,
    output out2);
    
    assign next_state[0] = ((state[0]|state[1]|state[2]|state[3]|state[4]|state[7]|state[8]|state[9])&!in);
    assign next_state[1] = (state[0]&in)|((state[8]|state[9])&in);
    assign next_state[2] = state[1]&in;
    assign next_state[3] = state[2]&in;
    assign next_state[4] = state[3]&in;
    assign next_state[5] = state[4]&in;
    assign next_state[6] = state[5]&in;
    assign next_state[7] = (state[6]&in)|(state[7]&in);
    assign next_state[8] = state[5]&!in;
    assign next_state[9] = state[6]&!in;
    

    assign out1 = (state == 'b100000000)||(state == 'b1000000000);
    assign out2 = (state == 'b10000000)||(state == 'b1000000000);
endmodule

3异常问题：为什么结果不对，特殊状态下0x180、0先80，会有异常结果输出。