8.27 过一遍墙上知识点

1.整理python语法

2.整理eric 知识点

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1.time complexity of fibonacci

        O(2**n) -> Fib(recursion); 

        O(n) ->Fib(Iterative)

2.using stack to implement queue

3.pipeline

        3.1: delay:T

              throuput = N of inst/T

              frequency:1/T

        3.2:example with pipelined adders: 64bits data using two 32 bits adders

        3.3:Verilog code for pipeline:output of stage1 serving as input of stage2

4.logic design 

        4.1: adders

                 half adders: S=A^B, C=AB

                full adders: S=A^B^Ci, C=AB+(A^B)Ci

                Overflow

        4.2: (1+x)^2 => adders+ shifter

5.verif plan

       exmple 1: adders

        5.1.1: reset: 111--> reset

        5.1.2:functional check

                        A):0+1: 101+010/010+101 

                        B):0+0

                        C):1+1: overflow,  corner case

                        max pos--->111+111 

                        max neg--->100+100

          5.1.3:error case

                     Reset and +

        Example 2: async fifo

        5.2.1: reset:full -->reset

        5.2.2: functional check (+corner case)

                A) fifo

                B) CDC

                C) Gray code 

        5.2.3:error case 

                full->write

                empty->read

6.bit manipulation 

a) &

|

^

~(求负) 

!(false or True//1 or 0）

>>

<< 

b) power2/ count 1s?  !(x&(x-1))&&x， while x, x=x&(x-1), cnt+=1

c) n%2, n//2

d)bin(n)[2:]=0b1000:是个str，可以forloop

e)a='11' print int(a,2) =>3, a是个str，将它变成int

f)rev.bit_length() ,rev是int整数，对rev求bit长度

g) AB=(进位需要积累的量）^(第n位)*（该位的数）

7.SV constraint/unique/shuffle/ inside/->/cover group/coverpoint/cross

8.low power

        8.1: power

                8.1.1: dynamic power: 1/2*C(V^2)Af

                8.1.2: static power: -leakage

                8.1.3: short-circuit power: transition

                8.1.4:capacitive power: 0->1, 1->0

        8.2:delay

                8.2.1: Vdd/(Vdd-Vth)^a, Vdd, Vth

       8.3:Isub

                8.3.1: Isub~Vt~Temperature 

        8.4:performance ~f ~V

9.async fifo 电路图

Eda playground 可以用来练verilog

10.self_intro

1.courses 

1.1: vlsi design

1.2: computer architecture

2.work experience

2.1: scripts

1. multiple small ones 2. 1 big one

2.2:verify

1. Understand 2.new test cases 3.cam ip

11. why verif? 

1.new, growth space

2.flow

3.saw+hw

(2 minutes and slow/clear )

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朗读一面墙只需20分钟，东西还全都过脑子了

what？

累

why？

心理障碍

how？

每次读20分钟，休息5分钟

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古典音乐可以舒缓学习的紧张情绪

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