PFGA中有关RS232串口的模块分享

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前言

这篇文章主要分享FPGA中与RS232串口有关的三个实用模块，只稍微介绍一下每个模块的端口详情，便于大家直接调用。由于本人刚接触FPGA不久，所学知识可能不够透彻，若有错误，还望指正。

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一、串口数据发送模块

module  uart_tx
#(
parameter   Bps         =   'd9600      ,
parameter   clk_freq    =   'd50_000_000
)
(
input   wire            sys_clk,
input   wire            sys_rst_n,
input   wire    [7:0]   pi_data,
input   wire            pi_flag,

output  reg             tx

);

parameter       baud_cnt_max    =   clk_freq/Bps    ;

reg             work_en     ;
reg     [9:0]   data        ;
reg     [31:0]  baud_cnt    ;
reg             baud_flag   ;
reg     [3:0]   bit_cnt     ;

    
always@(posedge sys_clk , negedge sys_rst_n)
    if(sys_rst_n==1'd0)
        data<=10'd0;
    else if(work_en==1'd0&&pi_flag==1'd1)
        data<={
   1'd1,pi_data[7:0],1'd0};
    else
        data<=data;
    
always@(posedge sys_clk , negedge sys_rst_n)
    if(sys_rst_n==1'd0)
        work_en <= 1'd0;
    else if(bit_cnt==4'd9&&baud_flag==1'd1)
        work_en <= 1'd0;
    else if(pi_flag==1'd1)
        work_en <= 1'd1;
    else
        work_en <= work_en;

always@(posedge sys_clk , negedge sys_rst_n)
    if(sys_rst_n==1'd0)
        baud_cnt <= 1'd0;
    else if(baud_cnt==baud_cnt_max-1'd1)
        baud_cnt <= 1'd0;
    else if(work_en==1'd0)
        baud_cnt <= 1'd0;
    else
        baud_cnt <= baud_cnt+1'd1;

always@(posedge sys_clk , negedge sys_rst_n)
    if(sys_rst_n==1'd0)
        baud_flag <= 1'd0;
    else if(baud_cnt==1'd1)
        baud_flag <= 1'd1;
    else
        baud_flag <= 1'd0;

always@(posedge sys_clk , negedge sys_rst_n)
    if(sys_rst_n==1'd0)
        bit_cnt <= 1'd0;
    else if(bit_cnt==4'd9&&baud_flag==1'd1)
        bit_cnt <= 4'd0