数字电路第二次试验

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY DECODER38 IS
PORT(
        A2,A1,A0:IN STD_LOGIC;
        YOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END DECODER38;

ARCHITECTURE RTL OF DECODER38 IS
SIGNAL TEMP:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
 TEMP<=A2&A1&A0;  ##这个句子很有可能忘掉！！
 YOUT<= "11111110" WHEN TEMP="000" ELSE
        "11111101" WHEN TEMP="001" ELSE
        "11111011" WHEN TEMP="010" ELSE
        "11110111" WHEN TEMP="011" ELSE
        "11101111" WHEN TEMP="100" ELSE
        "11011111" WHEN TEMP="101" ELSE
        "10111111" WHEN TEMP="110" ELSE
        "01111111" WHEN TEMP="111" ELSE
        "11111111";  ##这里容易加when others，记住别加！！
END RTL;

---

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX41BUS IS
PORT(
        SEL1,SEL0:IN STD_LOGIC;
        A,B,C,D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        YOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END MUX41BUS;

ARCHITECTURE RTL OF MUX41BUS IS
SIGNAL TEMP:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
TEMP<=SEL1&SEL0;
WITH TEMP SELECT
YOUT<=A WHEN "00",
      B WHEN "01",
      C WHEN "10",
      D WHEN OTHERS;
END RTL;

---

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PRIENCODER83 IS
PORT(
        INDATA:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        YOUT:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END PRIENCODER83;

ARCHITECTURE RTL OF PRIENCODER83 IS
BEGIN
YOUT<= "000" WHEN INDATA(0)='0' ELSE
       "001" WHEN INDATA(1)='0' ELSE
       "010" WHEN INDATA(2)='0' ELSE
       "011" WHEN INDATA(3)='0' ELSE
       "100" WHEN INDATA(4)='0' ELSE
       "101" WHEN INDATA(5)='0' ELSE
       "110" WHEN INDATA(6)='0' ELSE
       "111" WHEN INDATA(7)='0' ELSE
       "ZZZ";
END RTL;

---

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY HALFADD IS
PORT(
        A,B:IN STD_LOGIC;
        S,CO:OUT STD_LOGIC);
END HALFADD;

ARCHITECTURE RTL OF HALFADD IS
BEGIN
    S<=A XOR B;
    CO<=A AND B;
END RTL;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY FULLADD01 IS
PORT(
        A,B,CIN:IN STD_LOGIC;
        S,CO:OUT STD_LOGIC
);
END FULLADD01;
ARCHITECTURE RTL OF FULLADD01 IS
SIGNAL S1,C1,S2,C2:STD_LOGIC;
COMPONENT HALFADD
PORT(
        A,B:IN STD_LOGIC;
        SUM,CO:OUT STD_LOGIC
);
END COMPONENT;
BEGIN
U1:HALLADD PORTMAP(A,B,S1,C1);
U2:HALLADD PORTMAP(S1,CIN,S2,C2);
S<=S2;
CO<=C1 OR C2;
RTL;