HDLbits Exams/2013 q2bfsm

Consider a finite state machine that is used to control some type of motor. The FSM has inputs x and y, which come from the motor, and produces outputs f and g, which control the motor. There is also a clock input called clk and a reset input called resetn.

The FSM has to work as follows. As long as the reset input is asserted, the FSM stays in a beginning state, called state A. When the reset signal is de-asserted, then after the next clock edge the FSM has to set the output f to 1 for one clock cycle. Then, the FSM has to monitor the x input. When x has produced the values 1, 0, 1 in three successive clock cycles, then g should be set to 1 on the following clock cycle. While maintaining g = 1 the FSM has to monitor the y input. If y has the value 1 within at most two clock cycles, then the FSM should maintain g = 1 permanently (that is, until reset). But if y does not become 1 within two clock cycles, then the FSM should set g = 0 permanently (until reset).

考虑一个用于控制某种电机的有限状态机。 FSM 有输入 x 和 y 来自电机，并产生输出 f 和 g 来控制电机。 还有一个称为 clk 的复位输入 resetn 。

FSM 必须按如下方式工作。 只要复位输入被置位，FSM 就停留在 开始状态，称为状态 A 。 当复位信号被置低时，则在下一个时钟之后 边沿 FSM 必须将输出 f 为 1 持续一个时钟周期。 然后 ，FSM 必须监控 x 输入。 当 x 在三个连续的时钟周期中产生值 1、0、1 时， g 应该 在下一个时钟周期设置为 1。 在保持 g = 1 的同时，FSM 必须监控 y 输入。 如果 y 在最多两个时钟周期内为 1，则 FSM 应保持 g = 1 永久（即，直到重置）。 但是如果 y 在两个时钟周期内没有变为 1，那么 FSM 应永久设置 g = 0（直到复位）。

这道题的关键在于理解题意，并画出状态转移图，就很容易实现了。

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状态转移图：

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实现：

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
); 
    
    parameter A=4'd0,B=4'd1,C=4'd2,D=4'd3,E=4'd4,F=4'd5,G=4'd6,H=4'd7,I=4'd8;
    reg [3:0] state,next_state;
    
    always@(posedge clk)begin
        if(!resetn)
            state<=A;
        else
            state<=next_state;
    end
    
    always@(*)begin
        case(state)
            A:next_state=F;
            F:next_state=B;
            B:next_state=x?C:B;
            C:next_state=x?C:D;
            D:next_state=x?E:B;
            E:next_state=y?H:G;
            G:next_state=y?H:I;
            H:next_state=H;
            I:next_state=I;
            default:next_state=B;
        endcase
    end
    
    
    assign f=(state == F);
    assign g=(state == E || state == H  || state == G);
    
endmodule